HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 29

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

Bits 7
Bits 6:0
Bits 7
Bit 6:0
Bits 7
Bits 6:0
Bits 7
Bit 6
Bit 5
Bits 3:4
Bit 2
Bit 1
Bit 0
Bit 7
Bits 6:0
Bits 7:4
Bits 3:0
Bits 7:5
Bits 4:0
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
AGC look up table data, unsigned.
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
AGC loop gain (0.xxxx - x.00000, 0 - 1.0000 range), nominally 0.7.
AGC RX_RF, This input drives the RX-RF control if AGC override Enable is set to 1.
When Polarity bit (CR26[6]) is zero:
1 = removes 30dB pad.
0 = inserts 30dB pad.
AGC RX_IF, This CR is input to RF-IF DAC if AGC override Enable (CR 26[2]) is set to 1.
AGC continuous update.
0 = disable, no updates during AGC freeze.
1 = allow updates during freeze AGC and AGC_lock.
See also CR17[7].
rxRFAGC polarity control.
0 = normal.
1 = invert.
AGC extra update disable. Allows final 32 sample update tweak after AGC_lock is declared.
0 = enable an extra update.
1 = disable extra update.
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
AGC override Enable.
0 = normal, disabled.
1 = enabled, CR25 controls receiver gain in both RF and IF via RXRF_AGC and RXIF_AGC lines.
AGC 2nd antenna power abort.
0 = AGC lock on 2nd antenna is required to finish antenna dwell.
1 = abort 2nd antenna lock search immediately if power is lower on 2nd antenna than on 1st antenna.
AGC Sat Step disable if within CR29[7:5] window.
0 = disable sat step.
1 = enable sat step.
RXRF AGC disable.
0 = normal.
1 = disables threshold.
RF AGC threshold (0–64 range). The RxRf_Agc pad is removed if the AGC voltage falls below this threshold.
Mid saturation attenuation (0-30 range).
NOTE: mid saturation attenuation is programmed as this value times 2. The mid and low attenuator steps will occur if the
number of I and Q saturations are greater than the mid and low saturation counts set by CR16.
low saturation attenuation (0–15 range).
AGC Saturation Block Level, 1xx.x, range 4.0 to 7.5 dB. Disable saturation attenuation step if less than or equal to this level.
AGC lock window negative side. (0–15.5 range) (this is the outer lock window)
NOTE: set as a positive number, logic will convert to negative.
CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC LOCK WINDOW NEGATIVE SIDE
CONFIGURATION REGISTER ADDRESS 28 (38h) R/W AGC LOW SAT ATTENUATOR
29
CONFIGURATION REGISTER ADDRESS 27 (36h) R/W AGC RF THRESHOLD
CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC RX_IF AND RF
CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC TABLE DATA
CONFIGURATION REGISTER 26 ADDRESS (34h) R/W AGC TEST MODES
CONFIGURATION REGISTER 24 ADDRESS (30h) R/W AGC LOOP GAIN
HFA3863