M50LPW116 STMicroelectronics, M50LPW116 Datasheet
M50LPW116
Available stocks
Related parts for M50LPW116
M50LPW116 Summary of contents
Page 1
... Embedded Byte Program and Block/Chip Erase algorithms – Status Register Bits PROGRAM and ERASE SUSPEND ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 30h April 2005 16 Mbit (2M x8, Boot Block) 3V Supply Low Pin Count Flash Memory Figure 1. Packages M50LPW116 TSOP40 ( 20mm 1/43 ...
Page 2
... M50LPW116 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram (LPC Interface Figure 3. Logic Diagram (A/A Mux Interface Table 1. Signal Names (LPC Interface Table 2. Signal Names (A/A Mux Interface Figure 4. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Memory Identification Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Low Pin Count (LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Input/Output Communications (LAD0-LAD3) ...
Page 3
... Program Suspend Status (Bit Block Protection Status (Bit Reserved (Bit 0 Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Lock Down General Purpose Input Register Table 12. Low Pin Count Register Configuration Map ( M50LPW116 3/43 ...
Page 4
... M50LPW116 Table 13. Lock Register Bit Definitions Table 14. General Purpose Input Register Definition PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 15. Program and Erase Times MAXIMUM RATING Table 16. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC AND AC PARAMETERS Table 17. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 18. LPC Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 19. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7 ...
Page 5
... DESCRIPTION The M50LPW116 Mbit (2Mb x8) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming, and fast erasing, an optional 12V power supply can be used to reduce the pro- gramming and the erasing times. ...
Page 6
... Figure 2. Logic Diagram (LPC Interface ID0-ID3 5 GPI0- GPI4 LFRAME M50LPW116 CLK IC RP INIT V SS Figure 3. Logic Diagram (A/A Mux Interface A0-A10 RC M50LPW116 6/43 Table 1. Signal Names (LPC Interface) LAD0-LAD3 LFRAME ID0-ID3 4 GPI0-GPI4 LAD0- LAD3 INIT TBL CLK ...
Page 7
... floating floating floating M50LPW116 RFU RFU LFRAME W INIT G RFU RB RFU DQ7 RFU DQ6 RFU DQ5 RFU DQ4 LAD3 DQ3 ...
Page 8
... Table 1.. The LPC address sequence is 32 bits long. The M50LPW116 responds to addresses mapped to the top of the 4 GByte memory space, from FFFF FFFFh. Address bits A31-A26 must be set to 1. For A25-A23 and A21, see set to 1 for array access, and to 0 for register ac- cess ...
Page 9
... Main 4 40 Main 4 39 Main 4 38 Main 4 37 Main 4 36 Main 4 35 Main 4 34 Main 4 33 Main 4 32 Main Note: For A21 and A23, see M50LPW116 100000h-10FFFFh 31 0F0000h-0FFFFFh 30 0E0000h-0EFFFFh 29 0D0000h-0DFFFFh 28 0C0000h-0CFFFFh 27 0B0000h-0BFFFFh 26 0A0000h-0AFFFFh 25 090000h-09FFFFh 24 080000h-08FFFFh 23 070000h-07FFFFh 22 060000h-06FFFFh 21 050000h-05FFFFh 20 040000h-04FFFFh 19 030000h-03FFFFh 18 020000h-02FFFFh ...
Page 10
... M50LPW116 Address/Address Multiplexed (A/A Mux) Signal Descriptions For the Address/Address Multiplexed (A/A Mux) Interface see Figure 3., and Table Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A20). They are latched during any bus operation by the Row/Col- umn Address Select input, RC ...
Page 11
... Erase operation. Block Protection. Block 10., for details on forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the Lock Registers. M50LPW116 6., and Figure 6., for a description of the Table 23., and Figure 10., for details on ...
Page 12
... M50LPW116 Table 5. LPC Bus Read Field Definitions Clock Clock Cycle Cycle Field Number Count 1 1 START CYCTYPE DIR 3-10 8 ADDR 11 1 TAR 12 1 TAR 13-14 2 WSYNC 15 1 RSYNC 16-17 2 DATA 18 1 TAR 19 1 TAR Figure 5. LPC Bus Read Waveforms CLK LFRAME LAD0-LAD3 START ...
Page 13
... The LPC Flash Memory drives LAD0-LAD3 to 1111b, 1111b O indicating a turnaround cycle. 1111b The LPC Flash Memory floats its outputs and the host takes N/A (float) control of LAD0-LAD3. CYCTYPE START ADDR DATA + DIR M50LPW116 Description Table 2.. TAR SYNC TAR AI04430 13/43 ...
Page 14
... M50LPW116 Address/Address Multiplexed (A/A Mux) Bus Operations The Address/Address Multiplexed (A/A Mux) Inter- face has a more traditional style interface. The sig- nals consist of a multiplexed address signals (A0- A10), data signals, (DQ0-DQ7) and three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory. ...
Page 15
... One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure the Quadruple Byte Program command. M50LPW116 Table 15.. 15., for a suggested flowchart on using is not 16., for a suggested flowchart on using ...
Page 16
... M50LPW116 Chip Erase Command. The Chip Erase Com- mand can be only used in A/A Mux mode to erase the entire chip at a time. Erasing should not be at- tempted when V is not can also be executed below V PP sult could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller ...
Page 17
... X 00h 1 X 01h 1 X 60h 1 X 2Fh 1 X C0h Consecutive Addresses, BA Any address in the Block. 1,2,3 and M50LPW116 3rd 4th Addr Data Addr Data must be consecutive addresses differing only for address 5th Addr Data 17/43 ...
Page 18
... M50LPW116 STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey differ- ent information and errors on the operation. To read the Status Register the Read Status Reg- ister command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued ...
Page 19
... M50LPW116 Bit 3 Bit 2 Bit 1 ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ...
Page 20
... M50LPW116 LOW PIN COUNT (LPC) INTERFACE CONFIGURATION REGISTERS When the Low Pin Count Interface is selected sev- eral additional registers can be accessed. These registers control the protection status of the Blocks and read the General Purpose Input pins. See ble 12. for an example of the Register Configura- tion map, valid for the boot memory, i ...
Page 21
... Manufacturer Code Register DEV_REG Device Code Register GPI_REG General Purpose Input Register Note: 1. This map is referred to the boot memory (ID0-ID3 floating or driven Low, V (1) Register Name , and A21,A23-A25 set to ‘1’). IL M50LPW116 Memory Default Access Address Value FFBFC002h 01h R/W FFBFA002h 01h ...
Page 22
... M50LPW116 Table 13. Lock Register Bit Definitions Bit Bit Name Value 7-3 ‘1’ 2 Read-Lock ‘0’ ‘1’ 1 Lock-Down ‘0’ ‘1’ 0 Write-Lock ‘0’ Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-34] Lock Register (T_MINUS34_LK) ...
Page 23
... Time to program four bytes. Table Interface Test Condition V = 12V ± 5% A/A Mux 12V ± 5% A/A Mux 12V ± 5% A/A Mux 12V ± (3) (3) M50LPW116 (1) Min Max Unit Typ 10 200 s (4) 200 sec (2) sec 0.1 5 0.4 5 sec 0.75 8 sec 1 10 sec 5 ...
Page 24
... M50LPW116 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 16 ...
Page 25
... Parameter 0 0 Input and Output AC Testing Waveform I O < > Output AC Tri-state Testing Waveform M50LPW116 Table 17., Designers should check that the op- Min Max 3.0 3 – ...
Page 26
... M50LPW116 Figure 8. A/A Mux Interface AC Testing Input Output Waveform Table 20. Impedance Symbol Parameter (1) Input Capacitance C IN (1) Clock Capacitance C CLK Recommended Pin (2) L PIN Inductance Note: 1. Sampled only, not 100% tested. 2. See PCI Specification 25° 1MHz. 26/ (3) Test Condition ...
Page 27
... LPC 3.6V, f(CLK) = 33MHz max LPC f(CLK) = 33MHz I = 0mA OUT 6MHz A/A Mux IH A/A Mux Program/Erase Controller Active 12V ± M50LPW116 Min Max 0.3 V –0.5 CC -0.5 0.8 1. 0.5 CC 0.2 V –0.5 CC ±10 CC 200 CC 20 100 0.9 V ...
Page 28
... M50LPW116 Figure 9. LPC Interface Clock Waveform Table 22. LPC Interface Clock Characteristics Symbol Parameter (1) t CLK Cycle Time CYC t CLK High Time HIGH t CLK Low Time LOW CLK Slew Rate Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested ...
Page 29
... Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current spec- ification. 2. Applies to all inputs except CLK. tCHQZ tCHQX FLOAT OUTPUT DATA Parameter Test Condition (2) (2) M50LPW116 tDVCH tCHDX VALID VALID INPUT DATA AI04431 Value Unit Min 2 ...
Page 30
... M50LPW116 Figure 11. Reset AC Waveforms RP, INIT W, G, LFRAME RB Table 24. Reset AC Characteristics Symbol Parameter INIT Reset Pulse Width PLPH INIT Low to Reset PLRH RP or INIT Slew Rate INIT High to LFRAME Low PHFL t RP High to Write Enable or Output PHWL t Enable Low PHGL Note: 1 ...
Page 31
... GHQX Note may be delayed CHQV tAVAV COLUMN ADDR VALID tAVCH tCHQV tGLQV tGLQX Test Condition – t after the rising edge of RC without impact on t GLQV M50LPW116 NEXT ADDR VALID tCHAX tGHQZ tGHQX VALID Value Min 250 Min 50 Min 50 Min ...
Page 32
... M50LPW116 Figure 13. A/A Mux Interface Write AC Waveforms Write erase or program setup A0-A10 R1 tCLAX tAVCL RC tWHWL tWLWH DQ0-DQ7 32/43 Write erase confirm or Automated erase valid address and data or program delay tAVCH tCHAX tCHWH tVPHWH tWHGL tWHRL tDVWH tWHDX D IN1 D IN2 Read Status ...
Page 33
... WHGL t Write Enable High to RB Low WHRL (1,2) Output Valid, RB High QVVPL Note: 1. Sampled only, not 100% tested. 2. Applicable seen as a logic input (V PP Test Condition Low PP < 3.6V). PP M50LPW116 Value Unit Min 100 ns Min 50 ns Min 5 ns Min 50 ns Min 50 ...
Page 34
... M50LPW116 PACKAGE MECHANICAL Figure 14. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 27. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data Symbol Typ 0.500 34/ ...
Page 35
... Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. M50LPW116 O -free and TBBA-free 2 3 M50LPW116 35/43 ...
Page 36
... M50LPW116 FLOWCHARTS AND PSEUDO CODES Figure 15. Program Flowchart and Pseudo Code Start Write 40h or 10h Write Address & Data Read Status Register YES YES YES LPC NO Interface Only YES End Note Status check of b1 (Protected Block following the correct command sequence ...
Page 37
... Loop Invalid Error ( Program Error (1, 2) M50LPW116 Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) – write Address 3 & Data 3 (3) – write Address 4 & Data 4 (3) (memory enters read status state after ...
Page 38
... M50LPW116 Figure 17. Program Suspend and Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write a read Command Read data from another address Write D0h Program Continues Note error occurs, the Status Register must be cleared before performing further Program/Erase operations. ...
Page 39
... Invalid Error (1) NO Command Sequence Error (1) NO Erase Error (1) M50LPW116 Chip Erase command: – write 80h – write 10h (memory enters read Status Register after the Chip Erase command) do: – read Status Register while invalid error: – ...
Page 40
... M50LPW116 Figure 19. Block Erase Flowchart and Pseudo Code Start Write 20h Write Block Address & D0h Read Status Register YES YES b4 YES YES LPC Interface Only YES End Note error is found, the Status Register must be cleared before further Program/Erase Controller operations. ...
Page 41
... Program Write D0h Erase Continues NO NO Erase Complete Write FFh Read Data M50LPW116 Program/Erase Suspend command: – write B0h – write 70h do: – read Status Register while Erase completed Program/Erase Resume command: – write D0h to resume erase – ...
Page 42
... M50LPW116 REVISION HISTORY Table 29. Revision History Date Version September 2001 -01 First Issue 12-Dec-2001 -02 Extensions to the descriptions on Quadruple Byte Programming 16-Jan-2002 -03 Device code announced: 30h 01-Mar-2002 -04 RFU pins must be left disconnected 30-Jul-2002 -05 Quadruple Byte Mode, in LPC mode, removed Revision numbering modified: a minor revision will be indicated by incrementing the 22-Nov-2002 5 ...
Page 43
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M50LPW116 43/43 ...