SAB C165-LM Infineon Technologies, SAB C165-LM Datasheet - Page 10
SAB C165-LM
Manufacturer Part Number
SAB C165-LM
Description
Manufacturer
Infineon Technologies
Datasheet
1.SAF_C165-LM.pdf
(77 pages)
Specifications of SAB C165-LM
Packages
PG-MQFP-100
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
2.0 KByte
Program Memory
0.0 KByte
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Table 2
Symbol Pin Nr
XTAL1
XTAL2
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.15
Data Sheet
TQFP
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin Definitions and Functions
Pin Nr
MQFP
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Input
Outp.
I
O
IO
O
I
O
I
I
I
I
I/O
I/O
O
I/O
O
O
I/O
O
Function
XTAL1:
XTAL2:
To clock the device from an external source, drive
XTAL1, while leaving XTAL2 unconnected.
Minimum and maximum high/low and rise/fall times
specified in the AC Characteristics must be
observed.
Port 3 is a 15-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 3 outputs can be
configured as push/pull or open drain drivers. The
Port 3 pins serve for following alternate functions:
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
T3IN
T2IN
MRST
MTSR
TxD0
RxD0
BHE
WRH
SCLK
CLKOUT
6
Input to the oscillator amplifier and input
to the internal clock generator
Output of the oscillator amplifier circuit.
GPT2 Timer T6 Toggle Latch Output
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 Ext. Up/Down Ctrl Input
GPT1 Timer T4
Count/Gate/Reload/Capture Input
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2
Count/Gate/Reload/Capture Input
SSC Master-Receive/Slave-Transmit
Input/Output
SSC Master-Transmit/Slave-Receive
Output/Input
ASC0 Clock/Data Output (Asyn./Sync.)
ASC0 Data Inp. (Asyn.) or In/Out (Sync)
Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe
SSC Master Cl. Output / Slave Cl. Input
System Clock Output (= CPU Clock)
V2.0, 2000-12
C165
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