IR3500VMPBF International Rectifier, IR3500VMPBF Datasheet
IR3500VMPBF
Specifications of IR3500VMPBF
Related parts for IR3500VMPBF
IR3500VMPBF Summary of contents
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DESCRIPTION The IR3500V Control IC combined with one or more xPhase3 MOSFET driver functions for a VR11.1 CPU VTT power supply. FEATURES • phase operation with matching Phase IC • 0.7% overall system set point accuracy • ...
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ORDERING INFORMATION Device IR3500V MTRPBF * IR3500V MPBF *Samples only ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any ...
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RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ V ≤ 7.5V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 CCL ELECTRICAL SPECIFICATIONS The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. Typical values represent the ...
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PARAMETER Soft Start and Delay Start Delay (TD1) Soft Start Time (TD2) VID Sample Delay (TD3) PGOOD Delay (TD4 + TD5) OC Delay Time V(IIN) – V(OCSET) = 500 mV SS/DEL to FB Input Offset With FB = 0V, adjust ...
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PARAMETER Over Voltage Protection (OVP) Comparators Threshold at Power-up Threshold during Normal Compare to V(VDAC) Operation OVP Release Voltage during Compare to V(VDAC) Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Propagation Delay to IIN Measure ...
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PARAMETER VCCL Regulator Amplifier Reference Feedback Voltage VCCLFB Bias Current VCCLDRV Sink Current UVLO Start Threshold UVLO Stop Threshold Hysteresis General VCCL Supply Current Note 1: Guaranteed by design, but not tested in production Note 2: VDAC Output is trimmed ...
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PIN DESCRIPTION PIN# PIN SYMBOL 1-8 VID7-0 VID0 are grounded. VID6 is pulled up. VID2~4 are inputs to VID converter. 9 ENABLE Enable input. A logic low applied to this pin puts the IC ...
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VCCLDRV Output of the VCCL regulator error amplifier to control external transistor. The pin senses 12V power supply through a resistor. 31 PGOOD Open collector output that drives low during startup and under any external fault condition. Indicates converter ...
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Frequency and Phase Timing Control The oscillator and system clock frequency is programmable from 250kHz to 9MHZ by an external resistor (ROSC). The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase ...
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This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio ...
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TM Body Braking In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; The slew rate of the inductor current can be significantly increased by ...
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The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can ...
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ENABLE VBIAS VCCL COMPARATOR ENABLE 250nS - BLANKING + INTEL DELAY 850mV 1.2V AMD COMPARATOR 800mV 1.14V + VCCLDRV - 80mV VCCL REGULATOR 120mV AMPLIFIER DISCHARGE VCCLFB + 4.0V COMPARATOR - 0.94 1.19V VCCL OUTPUT 0.86 0.2V COMPARATOR + VCCL ...
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Adaptive Voltage Positioning Adaptive voltage positioning is implemented needed to reduce the output voltage deviations during load transients and the power dissipation of the load at heavy load. The circuitry related to voltage positioning is shown in Figure 9. The ...
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The voltage at the VDRP pin is a buffered version of the share bus IIN and represents the sum of the DAC voltage and the average inductor current of all the phases. The VDRP pin is connected to the FB ...
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Figure 12 depicts the start-up sequence VR11 VID with boot voltage. If there is no fault, the SS/DEL pin will start charging when the enable crosses the threshold. The error amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. ...
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The delay is required since over-current conditions can occur as part of normal operation due to inrush current over-current occurs during soft start (before PGOOD is asserted), the SS/DEL voltage is regulated by the over current amplifier to ...
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Linear Regulator Output (VCCL) The IR3500V has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V by ...
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Open Voltage Loop Detection The output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. If any fault condition forces the error amplifier output above VCCL-1.08V for 8 switching cycles, the ...
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Pre-charging of converter output voltage may trigger OVP. If the converter output is pre-charged above 1.73V as shown in Figure 17, the ROSC/OVP pin voltage will be higher than 1.6V when VCCLDRV voltage reaches 1.8V. ROSC/OVP pin voltage will be ...
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VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) VCCL UVLO ROSC/OVP 1.6V Figure 16 - Over-voltage protection during power-up 12V VCC VCCL+0.7V VCCL+0.7V VCCLDRV 1.8V OUTPUT VOLTAGE (VOSEN+) 1.73V VCCL UVLO ROSC/OVP 1.6V Figure 17 - Over-voltage protection with ...
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VCC VCCL+0.7V VCCL+0.7V VCCLDRV OUTPUT 1.73V VOLTAGE (VOSEN+) VID + 0.13V VCCL UVLO VCCL - 1V ROSC/OVP 0.6V 3.92V (4V-0.08V) SS/DEL Figure 18 - Over-voltage protection with pre-charging converter output VID + 0.13V <Vo < 1.73V VID (FAST VDAC) ...
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Open Remote Sense Line Protection If either remote sense line VOSEN+ or VOSEN- or both are open, the output of remote sense amplifier (VO) drops. The IR3500V monitors VO pin voltage continuously voltage is lower than 200 mV, ...
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Open Open Control Daisy Loop Fault Clearing Recycle VCCL Method Error Amp Disabled ROSC/OVP & IIN drive high until No OV clears SS/DEL Discharge Flags PGood 8 Delay? 32 Clock PHSOUT Pulses Pulses APPLICATIONS INFORMATION DESIGN PROCEDURE Oscillator Resistor Rosc ...
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The minimum over-current fault latch delay time quantified OCDEL VDAC Slew Rate Programming Capacitor C ...
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OCSET V ⋅ D I Where; I =Over current limit, n=Number of phases, K LIMIT G =Gain of the current sense amplifier D=Vo/V , m=Maximum integer ...
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V (max the above equation min) and V I above condition is not satisfied there is a need to use a device with higher β be used instead of a single NPN transistor. Thermistor R and ...
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For applications where AVP is not required, the compensation is the same as for the regular voltage mode control. For converters using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency, type III compensation is required as ...
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optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. CP1 A ceramic capacitor between 10pF and 220pF is usually ...
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PCB LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. • Dedicate at least one middle layer for a ground plane LGND. ...
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PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting. • Lead land length should be equal to maximum part ...
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SOLDER RESIST • The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non ...
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STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 32L MLPQ ( Body) – θ IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 www.irf.com Page 24.4 C/W, θ =0. Data and ...