MAX9157 Maxim, MAX9157 Datasheet - Page 8

• Manufacturer Part Number: MAX9157
• Description: The MAX9157 is a quad bus LVDS (BLVDS) transceiver for heavily loaded, half-duplex multipoint buses
• Manufacturer: Maxim

The MAX9157 is a four-channel, 200Mbps, 3.3V BLVDS
transceiver in 32-lead TQFP and QFN packages, ideal
for driving heavily loaded multipoint buses, typically 16
to 20 cards plugged into a backplane. The MAX9157
receivers accept a differential input and have a fail-safe
input circuit. The devices detect differential signals as
low as 100mV and as high as V
The MAX9157 driver outputs use a current-steering
configuration to generate a 9.25mA to 17mA output
current. This current-steering approach induces less
ground bounce and no shoot-through current, enhanc-
ing noise margin and system speed performance. The
outputs are short-circuit current limited.
The MAX9157 current-steering output requires a resis-
tive load to terminate the signal and complete the trans-
mission loop. Because the devices switch the direction
of current flow and not voltage levels, the output volt-
age swing is determined by the value of the termination
resistor multiplied by the output current. With a typical
15mA output current, the MAX9157 produces a 405mV
output voltage when driving a bus terminated with two
54Ω resistors (15mA
determined by the direction of current flow through the
termination resistor.
The fail-safe feature of the MAX9157 sets the output
high when the differential input is:
• Open
• Undriven and shorted
• Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the outputs and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when driver output is in
high impedance. A shorted input can occur because of
a cable failure.
When the input is driven with a differential signal with a
common-mode voltage of 0.05V to 2.4V, the fail-safe
circuit is not activated. If the input is open, undriven
and shorted, or undriven and parallel terminated, an
internal resistor in the fail-safe circuit pulls both inputs
above V
forcing the outputs high (Figure 1).
Quad Bus LVDS Transceiver
8
_______________________________________________________________________________________
CC
- 0.3V, activating the fail-safe circuit and
✕
Detailed Description
Fail-Safe Receiver Inputs
27Ω = 405mV). Logic states are
CC
.
The characteristic impedance of a differential PC board
trace is uniformly reduced when equal capacitive loads
are attached at equal intervals (provided the transition
time of the signal being driven on the trace is longer
than the delay between loads). This kind of loading is
typical of multipoint buses where cards are attached at
1in or 0.8in intervals along the length of a backplane.
The reduction in characteristic impedance is approxi-
mated by the following formula:
where:
Z
impedance
Co = unloaded trace capacitance (pF/unit length)
C
N = number of capacitive loads
L = trace length
For example, if Co = 2.5pF/in, C
18in, and Z
tial impedance is:
In this example, capacitive loading reduces the charac-
teristic impedance from 120Ω to 54Ω. The load seen by
Figure 1. Internal Fail-Safe Circuit
DIFF
L
= value of each capacitive load (pF)
-unloaded = unloaded differential characteristic
DO_+/RIN_+
D0_-/RIN_-
Z
SQRT [2.5pF / (2.5pF + 18 x 10pF / 18in)]
ZDIFF-loaded = 54Ω
DIFF
Z
SQRT [Co / (Co + N
DIFF
DIFF
-loaded = 120Ω
R
R
-unloaded = 120Ω, the loaded differen-
IN1
IN1
-loaded = Z
R
Effect of Capacitive Loading
IN2
V
CC
V
CC
- 0.3V
DIFF
✕
✕
-unloaded
L
C
= 10pF, N = 18, L =
L
/ L)]
MAX9157
✕
RO_