AD8322ARU-REEL Analog Devices Inc, AD8322ARU-REEL Datasheet - Page 7

• Manufacturer Part Number: AD8322ARU-REEL
• Description: IC LN DVR CATV COARS-STP 28TSSOP
• Manufacturer: Analog Devices Inc
• Type: Line Driver, Transmitterr

Specifications of AD8322ARU-REEL

• Rohs Status: RoHS non-compliant
• Applications: Modems, Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• For Use With: AD8322-EVAL - BOARD EVAL FOR AD8322

APPLICATIONS
General Application
The AD8322 is primarily intended for use as the upstream power
amplifier (PA) in DOCSIS (Data Over Cable Service Interface
Specifications) certified cable modems and CATV set-top boxes.
Upstream data is modulated in QPSK or QAM format. This is
done with DSP or a dedicated QPSK/QAM modulator. The
amplifier receives its input signal from the QPSK/QAM modula-
tor or from a DAC. In either case the signal must be low-pass
filtered before being applied to the amplifier. Because the distance
from the cable modem to the central office will vary with each
subscriber, the AD8322 must be capable of varying its output
power by applying gain or attenuation to ensure that all signals
arriving at the central office are of the same amplitude. The
upstream signal path contains components such as a transformer
and diplexer that will result in some amount of power loss. There-
fore, the amplifier must be capable of providing enough power
into a 75 Ω load to overcome these losses without sacrificing the
integrity of the output signal.
Operational Description
The AD8322 is composed of three analog functions in the power-
up or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differen-
tial configuration, it is imperative that the input signals be 180
degrees out of phase and of equal amplitudes. This will ensure
the proper gain accuracy and harmonic performance. The preamp
stage drives a DAC, which provides the bulk of the AD8322’s
attenuation (7 bits or 42.14 dB). The signals in the preamp and
DAC gain blocks are differential to improve the PSRR and linear-
ity. A differential current is fed from the DAC into the output
stage, which amplifies these currents to the appropriate levels
necessary to drive a 75 Ω load. The output stage utilizes negative
feedback to implement a differential 75 Ω output impedance.
This eliminates the need for external matching resistors.
SPI Programming and Gain Adjustment
Gain programming of the AD8322 is accomplished using a serial
peripheral interface (SPI) and three digital control lines, DATEN,
SDATA, and CLK. To change the gain, eight bits of data are
streamed into the serial shift register through the SDATA port.
The SDATA load sequence begins with a falling edge on the
DATEN pin, thus activating the CLK line. Although the CLK
line is now activated, no change in gain is observed. With the
CLK line activated, data on the SDATA line is clocked into the
serial shift register, Most Significant Bit (MSB) first, on the
rising edge of each CLK pulse. A rising edge on the DATEN line
latches the contents of the shift register into the attenuator core
resulting in a well-controlled change in the output signal level.
The serial interface timing for the AD8322 is shown in Fig-
ures 2 and 3. The programmable gain range of the AD8322 is
–12.64 dB to +29.5 dB and scales 6.02 dB for each major carry.
Because the AD8322 was characterized with a TOKO transformer,
the stated gain values already take into account the losses asso-
ciated with the transformer. Valid gain codes are the major carries
from decimal 1–128 (decimal values 1, 2, 4, 8, 16, 32, 64, 128).
The resulting gain for each code can be seen in Table I. Although
the AD8322 is designed for use with the previous eight codes,
the intermediate codes can be used.
The gain transfer function is as follows:
where A
of the 8-bit word.
Figure 4 shows the gain characteristic for all possible values
(except 0) in an 8-bit word. Code 0 may be used if more
feedthrough isolation is required. It typically provides –85 dB of
isolation across the 5 MHz to 65 MHz upstream band.
Input Bias, Impedance, and Termination
The V
V
differential input impedance is approximately 235 Ω while the
single-ended input impedance is 210 Ω. If the AD8322 is being
operated in a single-ended input configuration with a desired
input impedance of 75 Ω, the V
terminated as shown in Figure 5. For input impedances other
than 75 Ω, the value of R1 in Figure 5 can be calculated using
the following equation:
CC
A
A
V
V
/2, therefore the input signal should be ac-coupled. The
Z
= 20 × LOG (0.2332 × CODE) for 1 ≤ CODE ≤ 128
= 29.5 dB for CODE ≥ 128
IN+
IN
–10
–15
–20
35
30
25
20
15
10
–5
V
5
0
and V
= 1 210
is the gain in dB and CODE is the decimal equivalent
0
R
IN–
32
inputs have a dc bias level of approximately
R1 = 118
Z
IN
64
= 75
GAIN CODE – Decimal
96
IN+
128
and V
AD8322
160
IN–
192
inputs should be
AD8322
224
256