MAX9597CTI+T Maxim Integrated Products, MAX9597CTI+T Datasheet - Page 16

• Manufacturer Part Number: MAX9597CTI+T
• Description: IC AUD/VID INTERACE 28TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Audio/Video Interfacer

Specifications of MAX9597CTI+T

• Applications: DVD, Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power Audio/Video Interface
for Single SCART Connectors
The fast-switching signal was originally used to switch
between CVBS and RGB signals on a pixel-by-pixel
basis so that on-screen display (OSD) information
could be inserted. Since modern set-top box decoder
chips have integrated OSD circuitry, there is no need to
create OSD information using the older technique.
Now, the fast-switching signal is just used to switch
between CVBS and RGB signal sources.
Set the source of the fast-switching signal by writing to
bits 4 and 3 of register 07h. The fast-switching signal to
the TV SCART connector can be enabled or disabled
by bit 1 of register 0Dh. See Tables 9 and 11.
The MAX9597 features an I
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facili-
tate communication between the MAX9597 and the mas-
ter at clock rates up to 400kHz. Figure 4 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. A master
device writes data to the MAX9597 by transmitting a
START (S) condition, the proper slave address with the
R/W bit set to 0, followed by the register address and
then the data word. Each transmit sequence is framed
by a START and a STOP (P) condition. Each word trans-
mitted to the MAX9597 is 8 bits long and is followed by
Table 3. Slave Address
Figure 4. I
16
DEV_ADDR
______________________________________________________________________________________
SDA
SCL
GND
V
SDA
SCL
VID
2
t
HD, STA
C Serial-Interface Timing Diagram
CONDITION
START
B7
1
1
1
1
t
LOW
B6
0
0
0
0
t
R
2
C/SMBus™-compatible,
t
t
SU, DAT
HIGH
B5
0
0
0
0
I
t
2
F
C Serial Interface
Fast Switching
B4
1
1
1
1
t
HD, DAT
B3
0
0
1
1
t
SU, STA
B2
1
1
0
0
START CONDITION
an acknowledge clock pulse. A master reads from the
MAX9597 by transmitting the slave address with the R/W
bit set to 0, the register address of the register to be
read, a REPEATED START (Sr) condition, the slave
address with the R/W bit set to 1, followed by a series of
SCL pulses. The MAX9597 transmits data on SDA in
sync with the master-generated SCL pulses. The master
acknowledges receipt of each byte of data. Each read
sequence is framed by a START or REPEATED START
condition, an acknowledge or a not acknowledge, and a
STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500Ω, is required on the SDA bus. SCL operates as
only an input. A pullup resistor, typically greater than
500Ω, is required on SCL if there are multiple masters on
the bus, or if the master in a single-master system has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX9597 from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
REPEATED
SMBus is a trademark of Intel Corp.
B1
0
1
0
1
t
HD, STA
R/W
R/W
R/W
R/W
B0
WRITE ADDRESS
t
SP
(HEX)
9Ah
94h
96h
98h
t
SU, STO
CONDITION
STOP
READ ADDRESS
t
BUF
CONDITION
Bit Transfer
(HEX)
START
9Bh
95h
97h
99h