ISL98001CQZ-170 Intersil, ISL98001CQZ-170 Datasheet - Page 10

• Manufacturer Part Number: ISL98001CQZ-170
• Description: IC TRPL VIDEO DIGITIZER 128-MQFP
• Manufacturer: Intersil
• Type: Video Digitizerr

Specifications of ISL98001CQZ-170

• Applications: Digital TV, Displays, Digital KVM, Graphics Processing
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
CLOCKINV
HSYNC
VSYNC
HSYNC
VSYNC
RGB
RGB
XCLK
DATACLK
DATACLK
SYMBOL
XTAL
SOG
SOG
SADDR
RESET
XTAL
R
R
G
G
HS
B
B
G
G
R
B
R
B
SDA
SCL
P
S
P
S
P
S
IN
IN
IN
IN
IN
IN
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
OUT
GND
GND
OUT
OUT
IN
IN
1
2
1
1
2
2
IN
IN
IN
IN
IN
1
2
1
2
1
1
2
2
IN
MQFP PIN #(s)
100-107
112-119
90-97
80-87
68-75
55-62
121
122
125
12
19
13
14
33
44
22
24
28
25
26
34
45
41
46
39
40
47
48
50
49
7
10
Analog input. Red Channel 1. DC couple or AC couple through 0.1µF.
Analog input. Green Channel 1. DC couple or AC couple through 0.1µF.
Analog input. Blue Channel 1. DC couple or AC couple through 0.1µF.
Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as Channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
Analog input. Sync on Green. Connect to G
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND
signal through a 680Ω series resistor.
Digital input, 5V tolerant, 500mV hysteresis. Connect to Channel 1's VSYNC signal.
Analog input. Red Channel 2. DC couple or AC couple through 0.1µF.
Analog input. Green Channel 2. DC couple or AC couple through 0.1µF.
Analog input. Blue Channel 2. DC couple or AC couple through 0.1µF.
Analog input. Ground reference for the R, G, and B inputs of Channel 2 in the DC coupled configuration.
Connect to the same ground as Channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
Analog input. Sync on Green. Connect to G
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND
signal through a 680Ω series resistor.
Digital input, 5V tolerant, 500mV hysteresis. Connect to Channel 2's VSYNC signal.
Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during
VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to D
unused.
Digital input, 5V tolerant, active low, 70kΩ pullup to V
the ISL98001. This pin is not necessary for normal use and may be tied directly to the V
Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
3.3V digital output. Buffered crystal clock output at f
system components.
Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
3.3V digital output. Red channel, primary pixel data. 56k pulldown when three-stated.
3.3V digital output. Red channel, secondary pixel data. 56k pulldown when three-stated.
3.3V digital output. Green channel, primary pixel data. 56k pulldown when three-stated.
3.3V digital output. Green channel, secondary pixel data. 56k pulldown when three-stated.
3.3V digital output. Blue channel, primary pixel data. 56k pulldown when three-stated.
3.3V digital output. Blue channel, secondary pixel data. 56k pulldown when three-stated.
3.3V digital output. Data clock output. Equal to pixel clock rate in 24-bit mode, one half of pixel clock rate in
48-bit mode.
3.3V digital output. Inverse of DATACLK.
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals).
ISL98001
IN
IN
1 through a 0.01µF capacitor in series with a 500Ω resistor.
1 through a 0.01µF capacitor in series with a 500Ω resistor.
DESCRIPTION
XTAL
D
. Take low for at least 1µs and then high again to reset
or f
P-P
P-P
XTAL
A
A
centered around 0.5V.
centered around 0.5V.
/2. May be used as system clock for other
.
.
A
A
. Connect to Channel 1's HSYNC
. Connect to Channel 2's HSYNC
D
supply.
September 21, 2010
GND
FN6148.5
if