LMH0026MH/NOPB National Semiconductor, LMH0026MH/NOPB Datasheet - Page 7

• Manufacturer Part Number: LMH0026MH/NOPB
• Description: IC RECLOCKER SDI HD/SD 20-TSSOP
• Manufacturer: National Semiconductor
• Type: Reclockerr

Specifications of LMH0026MH/NOPB

• Applications: Digital Video
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH0026MH

LOCK DETECT
SERIAL DATA CLOCK/SERIAL DATA 2 OUTPUT
The Serial Data Clock/Serial Data 2 Output is controlled by
the SCO_EN input and provides either a second retimed se-
rial data output or a low jitter differential clock output appro-
priate to the serial data rate being processed. When operating
as a serial clock output, the rising edge of the clock will be
positioned within the corresponding serial data bit interval
within 10% of the center of the data interval.
Differential output SCO/SDO2 functions as the second serial
data output when the SCO_EN input is a logic-low level. This
output functions as the serial data-rate clock output when the
SCO_EN input is a logic-high level. The SCO_EN input has
an internal pull-down device and the default state of SCO_EN
is low (serial data output 2 enabled). SCO/SDO2 is muted
when the OUTPUT MUTE input is a logic low level. When the
Bypass mode is activated and this output is functioning as a
serial clock output, the output will also be muted. If an unsup-
ported data rate is used while in Auto Bypass mode with this
output functioning as a serial clock output, the output is in-
valid.
Control Inputs and Indicator
Outputs
LOCK DETECT
The Lock Detect (LD) output, when high, indicates that data
is being received and the PLL is locked. LD may be connected
SD
The SD output indicates that the LMH0026 is locked and pro-
cessing SD data rates. It may be used to control another
device such as the LMH0002 cable driver. When this output
is high it indicates that the data rate is 270 Mbps. The SD
output is a registered function and is only valid when the PLL
X
0
1
0
1
OUTPUT MUTE
LOCK DETECT
LOCK DETECT
FIGURE 2. Equivalent SDO Output Circuit (SDO, SDO, SCO/SDO2, SCO/SDO2)
1
1
0
BYPASS/AUTO BYPASS
TABLE 1. Control Functionality
X
X
X
0
0
7
PLL unlocked, reclocker bypassed
PLL locked to supported data rate, reclocker not bypassed
Outputs muted
Outputs muted
PLL locked to supported data rate, reclocker not bypassed
to the OUTPUT MUTE input to mute the data and clock out-
puts when no data signal is being received. Note that when
the Bypass/Auto Bypass input is set high, Lock Detect will
remain low. See
OUTPUT MUTE
The OUTPUT MUTE input, when low, mutes the serial data
and clock outputs. It may be connected to Lock Detect or ex-
ternally driven to mute or un-mute the outputs. If OUTPUT
MUTE is connected to LD, then the data and clock outputs
are muted when the PLL is not locked. This function overrides
the Bypass function: see
internal pull-up device to enable the output by default.
BYPASS/AUTO BYPASS
The Bypass/Auto Bypass input, when high, forces the device
to output the data without reclocking it. When this input is low,
the device automatically bypasses the reclocking function
when the device is in an unlocked condition or the detected
data rate is a rate which the device does not support. Note
that when the Bypass/Auto Bypass input is set high, Lock
Detect will remain low. See
PASS has an internal pull-down device.
is locked and the Lock Detect output is high. When the PLL
is not locked (the Lock Detect output is low), the SD output
defaults to low. The SD output is undefined for a short time
after lock detect assertion or de-assertion due to a data
change on SDI. See
the relationship between SDI, Lock Detect, and SD.
Table
DEVICE STATUS
Figure 3
1.
Table
Table
for a timing diagram showing
30001809
1. OUTPUT MUTE has an
1. BYPASS/AUTO BY-
www.national.com