DS8007 Maxim, DS8007 Datasheet - Page 30

• Manufacturer Part Number: DS8007
• Description: The DS8007 multiprotocol dual smart card interface is a low-cost, dual smart card reader interface supporting all ISO 7816, EMV®, and GSM11-11 requirements
• Manufacturer: Maxim

Multiprotocol Dual Smart Card Interface
The timeout counter assists the host device in timing
real-time events associated with the communication pro-
tocols: the Work Wait Time (WWT), Block Waiting Time
(BWT), etc. The timeout counter registers count ETUs, so
the input clock to the timeout counter is derived from the
output of the programmable divided clock (per card PDR
register). The timeout counter requires the card be pow-
ered and have an active clock.
The timeout counter can operate as a single 24-bit
counter (TOR3–TOR1) or as separate 16-bit
(TOR3–TOR2) and 8-bit (TOR1) counters. The timeout
counters can be operated in either software mode or
start bit mode. The software mode is supported for the
16-bit and 24-bit counters. The start-bit mode is sup-
ported for all counter widths (8 bit, 16 bit, and 24 bit).
See Table 3.
In software mode, software configures the counter to a
starting value (while stopped) and starts the down
counter by writing the configuration value to the TOC
register. When the terminal count is reached (0h), the
counter stops, the timeout flag is set, and an interrupt is
generated. If the software counter does not reach the
terminal count, it must be stopped before loading a
new value into the associated TORx counter registers.
Table 3. Timeout Counter Configurations
30
TOC VALUE
______________________________________________________________________________________
00h
05h
61h
65h
68h
Timeout Counter Operation
TOR3
Software
Software
Stopped
TOR2
Stopped
Software
Software Mode
Bit/Autoreload
Bit/Autoreload
Stopped
TOR1
Start
Start
All counters are stopped.
Counters 3 and 2 are stopped. Counter 1 continues in start-
bit/autoreload mode for both transmission and reception.
Counter 1 is stopped. Counters 3 and 2 form a 16-bit counter
operating in software mode. The counter is stopped by writing 00h to
the TOC register, and must be stopped before reloading new values
in TOR3 and TOR2 registers.
Counters 3 and 2 form a 16-bit counter operating in software mode.
Writing 05h to the TOC register before reloading new values in
TOR2/TOR3 stops the counters. Counter 1 is operated in start-
bit/autoreload mode. The TOR1 register may not change during the
count. The 16-bit counters are stopped by setting TOC = 05h. Both
counters are stopped by setting TOC = 00h.
Counters 1, 2, and 3 form a 24-bit counter operating in software
mode. The counter starts after the command is written to the TOC
register, and is stopped by setting TOC = 00h. TOR3, TOR2, TOR1
cannot be changed without stopping the counter first.
It is possible to stop and start the 16-bit software
counter while leaving the 8-bit counter enabled (e.g.,
TOC = 65h ↔ 05h, TOC = E5h ↔ 85h, etc.).
If a compatible software mode command is written to the
TOC register before the terminal count is reached (e.g.,
write 61h to TOC register while the 65h TOC command is
running or vice versa), the new command is ignored (still
software mode), but the TOC register is updated with the
new command, and the counter continues to count until
the terminal count is reached, the respective timeout
flag(s) is set, and an interrupt is generated.
When configured to start-bit mode, counting starts (and
restarts for the 16-bit and 24-bit counters) when a
START bit is detected on the active card interface I/Ox
pin. When the terminal count is reached, the 8-bit
autoreload counter begins counting from the previously
programmed start value, while a 16-bit counter or 24-bit
counter stops when terminal count is reached. If the
terminal count is reached, the timeout flag is set and an
interrupt is generated. The 8-bit autoreload TOR1 regis-
ter cannot be modified during a count. The 16-bit and
24-bit counter registers can be modified during a count
without affecting the current count. The new register
data is used on the next START bit detection.
DESCRIPTION
Start-Bit Mode