73S8024C Maxim, 73S8024C Datasheet - Page 8

• Manufacturer Part Number: 73S8024C
• Description: The 73S8024C is a single smart card interface IC, compliant to the electrical requirements of ISO 7816-3 and EMV 4
• Manufacturer: Maxim

73S8024C Data Sheet
6 Voltage Supervision
Two voltage supervisors constantly check the level of the voltages V
sequence is triggered upon a fault of any of these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. V
range for the interface with the system controller. The V
ISO-7816-3 sequencer at power-on, and also to deactivate the card at power-off or upon a fault. The
voltage threshold of the V
may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the
SO package, pin 17 in the QFN package) is used to connect an external resistor R
the V
An alternative (more accurate) method of adjusting the V
R3 from the pin to supply and R1 from the pin to ground (see
voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx
is defined as R1/(R1+R3) and is calculated as:
To determine the values of R1 and R3, use the following formulas:
Taking the example above, where a V
Solving for R3 gives:
Solving for R1 gives:
Using standard 1% resistor values gives R3 = 191 kΩ and R1 = 115 kΩ. These values give an equivalent
resistance of Kx = 0.376, a 0.3% error.
If the 2.3 V default threshold is used, this pin must be left unconnected.
7 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8024C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from
the host controller).
The host controller invokes the power down state when it is desirable to save power. The signals PRES
and PRES remain functional in PD mode such that a card insertion sets OFF high. The micro-controller
must then set PWRDN low and wait for the internal stabilization time prior to starting any card session
(prior to turning CMDVCC low).
Resumption of the normal mode occurs at approximately 10 ms (stabilization of the internal oscillators
and reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, OFF can be used as an indication that the circuit has completed its
recovery from the power down state. OFF will go high at the end of the stabilization period. Should
CMDVCC go low during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not be
taken into account and the card interface will remain inactive. Since CMDVCC is taken into account on
its edges, it should be toggled high and low again after the 10 ms to activate a card.
Figure 2
the power down function is not used.
8
DD
R
Kx = (2.649 / V
R3 = 72000 / Kx
fault voltage to another value, V
 Kx = (2.649 / 2.7) - 0.6042 = 0.377.
illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
EXT
= 180 kΩ / (V
TH
 R3 = 72000 / 0.377 = 191 kΩ.
 R1 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ.
) - 0.6042 where V
DD
DDF
voltage supervisor is internally set by default to 2.3 V nominal. However, it
- 2.33)
R1 = R3*(Kx / (1 – Kx))
DD
DDF
fault threshold voltage of 2.7 V is desired, solving for Kx gives:
. The resistor value is defined as follows:
TH
is the desired new threshold voltage.
DD
DD
Voltage supervisor is also used to initialize the
fault voltage is to use a resistive network of
Figure 9
DD
). In order to set the new threshold
and V
CC
DD
. A card deactivation
also defines the voltage
EXT
to ground to raise
DS_8024C_023
Rev. 1.3