MAXQ3181 Maxim, MAXQ3181 Datasheet - Page 56

• Manufacturer Part Number: MAXQ3181
• Description: The MAXQ3181 is a dedicated electricity measurement front-end that collects and calculates polyphase voltage, current, active power and energy, and many other metering parameters of a polyphase load
• Manufacturer: Maxim

Low-Power, Active Energy, Polyphase AFE
Each phase has a local register that contains copies of
the OC, OV, UV, NOZX, and DCHA bits. Thus, to deter-
mine which phase(s) have exception conditions
requires four reads: the IRQ_FLAG register to deter-
mine which conditions are active that are causing the
interrupt to occur, and then a read to A.FLAGS,
B.FLAGS, and C.FLAGS to determine which of the
phases have the indicated condition.
Finally, each phase has a pair of local registers that
contain overflow flags for each energy accumulator. If
the EOVF bit is set in the IRQ_FLAG register, the host
should then read the A.EOVER, B.EOVER, and
C.EOVER registers to determine which of the phases
have overflow conditions.
56
OV: The RMS voltage on one or more of the phases
over the most recent DSP cycle has exceeded the
value set in the OVLVL register.
UV: The RMS voltage on one or more of the phases
over the most recent DSP cycle has failed to exceed
the value set in the UVLVL register.
NOZX: Zero crossings were not detected on one or
more of the phases. The detection time is defined in
the NZX_TIMO register. The resolution for the
NZX_TIMO register is the duration of one ADC sam-
ple time (nominally 40μs).
DCHA: Tells the host processor that the direction of
net real energy flow on one of the three phases has
changed during the current DSP cycle as compared
to the previous DSP cycle.
DSPRDY: Indicates the latest DSP cycle has just
completed.
DSPOR: Indicates that the processing for the previ-
ous DSP cycle had not been completed before the
current DSP cycle became available for processing.
This overflow indication should never be seen in the
default configuration; however, under some condi-
tions (faster ADC rate, slower CPU clock) the pro-
cessing requirements may exceed the number of
CPU cycles available for DSP processing. Under
these circumstances, the clock rate may be
increased, the ADC rate may be reduced (that is,
the R_ADCRATE register may be increased).
Note that when DSPOR becomes set, all DSP calcu-
lations as well as the pulse output are invalidated.
The appropriate host response is to take the remedi-
al action described above and discard the current
set of DSP result values.
______________________________________________________________________________________
The MAXQ3181 detects overvoltage and overcurrent
events and can issue interrupt request signals to the
master when these events occur. The overvoltage level
can be programmed into the OVLVL register, while the
overcurrent level is determined by the OCLVL register.
Both OVLVL and OCLVL registers represent the bits
23:8 of the VRMS or IRMS registers. Any time the
MAXQ3181 detects the RMS-value exceeding a thresh-
old level, the OV or OC interrupt flag is set. If enabled,
any of these flags issues an interrupt request. All inter-
rupt flags are “sticky” bits—the MAXQ3181 never
clears them on its own unless a reset occurs. The inter-
rupt flags should be cleared by the master by writing
the appropriate register.
All energy calculations, including various threshold
checks, are performed internally in fixed format in meter
units. Therefore, the threshold values must be supplied
by the user in meter units as well. This section summa-
rizes how to convert real units (V, A, kWh, W, and kAh)
into meter units and vice versa.
The conversion factors are based on the settings of t
V
t
defined by the R_ADCRATE setting and system clock
frequency f
Default conditions are R_ADCRATE = 319, f
V
produces full-scale ADC output; defined by the hard-
ware voltage transducer ratio V
input voltage V
Default conditions are V
dependent.
I
produces full-scale ADC output; defined by the hard-
ware current transducer ratio I
input voltage V
Default conditions are V
dependent.
Meter units are defined with respect to the base para-
meters as shown in Table 5.
FR
FS
FS
FS
, and I
is full-scale current. This is the input current that
is analog scan frame timing. This parameter is
is full-scale voltage. This is the input voltage that
Meter Units to Real Units Conversion
FS
SYS
t
, defined by the user’s design.
FR
Overvoltage and Overcurrent Detection
:
FSADC
FSADC
= (R_ADCRATE + 1) x 8/f
V
I
FS
FS
:
:
= V
= V
FSADC
FSADC
FSADC
FSADC
= 1.024V. V
= 1.024V. I
TR
x V
x I
TR
TR
TR
and ADC full-scale
and ADC full-scale
SYS
SYS
TR
TR
is design
is design
= 8MHz.
FR
,