71M6513H Maxim, 71M6513H Datasheet - Page 41

• Manufacturer Part Number: 71M6513H
• Description: The 71M6513 and 71M6513H are highly integrated SoCs with an MPU core, RTC, flash, and LCD driver
• Manufacturer: Maxim

Physical Memory
Data bus address space is allocated to on-chip memory as shown in Table 54.
Flash Memory: The 71M6513 includes 64KB of on-chip flash memory. The flash memory is intended to primarily contain MPU
program code. In a typical application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O
RAM. On power-up, before enabling the CE, the MPU must copy these images to their respective memory locations.
The I/O RAM bit register FLASH66Z defines the pulse width for accessing flash memory. To minimize supply current draw,
this bit should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the flash memory.
The mass erase sequence is:
The page erase sequence is:
Writing to flash memory:
The MPU may write to the flash memory for non-volatile data storage or when implementing a boot-loader. The I/O RAM
register FLSH_PWE (flash program write enable, SFR B2[0]) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL =1. After the
write operation, FLSH_PWE must be cleared.
The original state of a flash byte is 0xFF (all bits are 1). Overwriting programmed flash cells with a different value usually re-
quires that the cell is erased first. Since cells cannot be erased individually, the page has to be copied to RAM, followed by a
page erase. After this, the page can be updated in RAM and then written back to the flash memory.
excluding the critical addresses from the write operation.
MPU RAM: The 71M6513 includes 2KB of static RAM memory on-chip (XRAM), which are backed-up by the battery plus 256-
bytes of internal RAM in the MPU core. The 2KB of static RAM are used for data storage during normal MPU operations.
CE DRAM: The CE DRAM is the data memory of the CE. The MPU can read and write the CE DRAM as the primary means of
data communication between the two processors.
CE PRAM: The CE PRAM is the program memory of the CE. The CE PRAM has to be loaded with CE code before the CE
starts operating. CE PRAM cannot be accessed by the MPU when the CE is running.
0000-FFFF
0000-07FF
1000-13FF
2000-20FF
3000-3FFF
Address
1.
2.
Note: The mass erase cycle can only be initiated when the ICE port is enabled.
1.
2.
(hex)
Writing to flash locations will affect the corresponding XRAM cells, i.e. 0x2000 to 0x20FF (I/O RAM), 0x0000 to
0x07FF (MPU RAM), plus CE DRAM and CE PRAM. It is critical to maintain the integrity of the cells 0x2000…0x2007
as a minimum (where important system settings are stored) during the flash-write operation. This can be achieved by
Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
Write pattern 0xAA to FLSH_ERASE (SFR address 0x94)
Write the page address to FLSH_PGADR (SFR address 0xB7[7:1]
Write pattern 0x55 to FLSH_ERASE (SFR address 0x94)
A Maxim Integrated Products Brand
Flash Memory
Technology
Static RAM
Static RAM
Static RAM
Static RAM
Memory
Battery-buffered
Memory Type
Non-volatile
© 2005-2011 Teridian Semiconductor Corporation
Volatile
Volatile
Volatile
Table 54: MPU Data Memory Map
Program and non-volatile
Configuration RAM
CE Program code
3-Phase Energy Meter IC
MPU data RAM
Typical Usage
(I/O RAM)
CE data
data
71M6513/71M6513H
DATA SHEET
Wait States
(at 5MHz)
0
0
5
0
5
SEPTEMBER 2011
Page: 41 of 104
Memory Size
(bytes)
64KB
2KB
1KB
4KB
256