DS80C400 Maxim, DS80C400 Datasheet - Page 48

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

facilitates the conversion of 4-Byte unsigned binary integers into floating point format.
operations supported by the math accelerator and their time of execution.
Table 11. Arithmetic Accelerator Execution Times
Table 12
The MA and MB registers must be loaded and read in the order shown for proper operation, although accesses to
any other registers can be performed between accesses to the MA or MB registers. An access to the MA, MB, or
MC registers out of sequence corrupt the operation, requiring the software to clear the MST bit to restart the math
accelerator state machine. See the descriptions of the MCNT0 and MCNT1 SFRs for details about how the shift
and normalize functions operate.
Table 12. Arithmetic Accelerator Sequencing
*Not performed for 16-bit numerator.
Load MA with dividend LSB.
Load MA with dividend LSB + 1
Load MA with dividend LSB + 2
Load MA with dividend MSB.
Load MB with divisor LSB.
Load MB with divisor MSB.
Poll the MST bit until cleared.
Read MA to retrieve the quotient MSB.
Read MA to retrieve the quotient LSB + 2
Read MA to retrieve the quotient LSB + 1
Read MA to retrieve the quotient LSB.
Read MB to retrieve the remainder MSB.
Read MB to retrieve the remainder LSB.
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.
Configure MCNT0/MCNT1 registers as required.
Poll the MST bit until cleared (9 machine cycles).
Read MA for result MSB.
Read MA for result LSB + 2.
Read MA for result LSB + 1.
Read MA for result LSB.
32-Bit Shift Left/Right
16-Bit/16-Bit Multiply
32-Bit/16-Bit Divide
16-Bit/16-Bit Divide
32-Bit Normalize
(9 machine cycles for 32-bit numerator)
(6 machine cycles for 16-bit numerator)
OPERATION
demonstrates the procedure to perform mathematical operations using the hardware math accelerator.
DIVIDE (32/16 or 16/16)
SHIFT RIGHT/LEFT
32-Bit Quotient, 16-Bit Remainder
16-Bit Quotient, 16-Bit Remainder
32-Bit Mantissa, 5-Bit Exponent
*
*
.
.
32-Bit Product
32-Bit Result
RESULT
*
*
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Load MB with multiplier LSB.
Load MB with multiplier MSB.
Load MA with multiplicand LSB.
Load MA with multiplicand MSB.
Poll the MST bit until cleared (6 machine cycles).
Read MA for product MSB.
Read MA for product LSB + 2.
Read MA for product LSB + 1.
Read MA for product LSB.
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.
Configure MCNT0.4–0 = 00000b.
Poll the MST bit until cleared (9 machine cycles).
Read MA for mantissa MSB.
Read MA for mantissa LSB + 2.
Read MA for mantissa LSB + 1.
Read MA for mantissa LSB.
Read MCNT0.4–MCNT0.0 for exponent.
EXECUTION TIME
36 t
24 t
24 t
36 t
36 t
CLCL
CLCL
CLCL
CLCL
CLCL
MULTIPLY (16 x 16)
NORMALIZE
Table 11
shows the