DS1375 Maxim, DS1375 Datasheet - Page 10

• Manufacturer Part Number: DS1375
• Description: The DS1375 digital real-time clock (RTC) is a low-power clock/calendar that does not require a crystal
• Manufacturer: Maxim

I
Bit 1/Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the SQW/INT pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0/Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the SQW/INT pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
The DS1375 supports a bidirectional I
transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiv-
ing data as a receiver. The device that controls the
message is called a master. The devices that are con-
trolled by the master are slaves. A master device that
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions must control the bus. The DS1375 operates as a
slave on the I
Figure 3. I
10
2
SDA
SCL
C Digital Input RTC with Alarm
Bit 7
____________________________________________________________________
0
IDLE
2
C Data Transfer Overview
CONDITION
START
2
C bus. Connections to the bus are made
Bit 6
ADDRESS
MSB FIRST
0
SLAVE
1–7
I 2 C Serial Data Bus
Status Register (0Fh)
R/W
8
Bit 5
0
2
ACK
C bus and data
9
Bit 4
MSB
0
1–7
REPEATED IF MORE BYTES
ARE TRANSFERRED
DATA
LSB
through the open-drain I/O lines SDA and SCL. Within
the bus specifications a standard mode (100kHz max
clock rate) and a fast mode (400kHz max clock rate)
are defined. The DS1375 works in both modes.
The following bus protocol has been defined (Figure 3):
•
•
Accordingly, the following bus conditions have been
defined:
8
Bit 3
0
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the data line’s
state from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the data line’s
state from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The data line’s state represents valid
data when, after a START condition, the data line is
stable for the duration of the high period of the
clock signal. The data on the line must be changed
Data transfer can be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high can be
interpreted as control signals.
ACK
9
Bit 2
MSB
1–7
0
DATA
Status Register (0Fh)
LSB
8
Bit 1
A2F
NACK
ACK/
9
STOP CONDITION
REPEATED START
Bit 0
A1F