DS1372 Maxim, DS1372 Datasheet
DS1372
Related parts for DS1372
DS1372 Summary of contents
Page 1
... Rev 0; 7/ 32-Bit, Binary Counter Clock with 64-Bit ID General Description The DS1372 is a 32-bit binary up counter and 24-bit down counter with a unique 64-bit ID. The counters, ID, configuration, and status registers are accessed using serial interface. The DS1372 includes a SQW/INT open-drain output that can output either a ...
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... Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... CC(MAX) Note 13: The DS1372 can detect any single SCL clock held low longer than T can receive a new START condition when SCL is held low for at least T tion the SDA output is released. The oscillator must be running for this function to work. _______________________________________________________________________________________ ...
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... CONTROL/ STATUS ÷4096 CLR 64-BIT ID ROM Pin Description ). Pin X1 is the input to the serial interface and is used serial interface. The SDA pin is SQW SQW/INT MUX MUX N INTCN 32-BIT COUNTER 24-BIT ALARM AF COUNTER DS1372 ACE or ...
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... Application Note 58: Crystal Considerations with Dallas Real-Time Clocks (RTCs external 32.768kHz oscil- lator can be used as the DS1372’s time base. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 is floated. The EOSC bit in the Control Register controls oscillator operation ...
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... AF bit in the Status Register, if the AF bit is not already set. If the AIE and INTCN bits are both set to a logic 1, the SQW/INT pin goes low and remains low until AF is written to logic 0. The counter is then Table 1. DS1372 Address Map ADDRESS REGISTER 00h ...
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... I C, 32-Bit, Binary Counter Clock with 64-Bit ID Special Purpose Registers The DS1372 has two additional registers that control the alarm counter and interrupts: Control Register (07h) and Status Register (08h). Bit # 7 6 Name ACE Reset 0 0 Control Register (07h) Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started ...
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... The CRC byte is gener- ated with the polynomial equal insufficient to sup- Figure 3). The DS1372 is manufactured such that no two devices contain an identical number in locations 0Ah–0Fh. The DS1372 supports a bidirectional I data transmission protocol (Figure 4). A device that sends data onto the bus is defined as a transmitter, and a device receiving data is defined as a receiver ...
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... CONDITION 2 Figure Data Transfer Overview conditions. The DS1372 operates as a slave on the I bus. Connections to the bus are made through the SCL input and open-drain SDA I/O lines. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined ...
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... Data is transferred with the most significant bit (MSB) first. The DS1372 can operate in the following two modes: 1) Slave receiver mode (DS1372 write mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted ...
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... A is compared to the value on the AD0 pin. After receiving and decoding the slave address byte, the device outputs an acknowledge on the SDA line. The DS1372 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not writ- ...
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... Thermal Resistance (Junction to Ambient) θ Thermal Resistance (Junction to Case) θ Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...