DS1371 Maxim, DS1371 Datasheet - Page 3

• Manufacturer Part Number: DS1371
• Description: The DS1371 is a 32-bit binary counter that is designed to continuously count time in seconds
• Manufacturer: Maxim

AC ELECTRICAL CHARACTERISTICS
(V
SCL Clock Frequency (Note 9)
Bus Free Time Between STOP and
START Conditions
Hold Time (repeated) START Condition
(Note 10)
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 11, 12)
Data Setup Time (Note 13)
Start Setup Time
Rise Time of Both SDA and SCL
Signals (Note 9)
Fall Time of Both SDA and SCL Signals
(Note 9)
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
(Note 7)
Pulse Width of Spikes that Must be
Suppressed by the Input Filter (Note 14)
Watchdog Strobe (WDS) Pulse Width
Oscillator Stop Flag (OSF) Delay
(Note 8)
Note 1: All voltages are referenced to ground.
Note 2: SCL and WDS only.
Note 3: SDA and SQW/INT.
Note 4: Limits at -40°C are guaranteed by design and not production tested.
Note 5: I
Note 6: Specified with WDS input and I
Note 7: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 8: The parameter t
Note 9: A fast mode device can be used in a standard mode system, but the requirement t
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
Note 12: The maximum t
Note 13: C
Note 14: This parameter is not production tested.
CC
= 1.7V to 5.5V, T
CCA
≤ V
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of
the SCL signal, it must output the next data bit to the SDA line t
bridge the undefined region of the falling edge of SCL.
B
—SCL clocking at max frequency = 400kHz. WDS inactive.
—total capacitance of one bus line in pF.
B
CC
≤ V
PARAMETER
CCMAX
.
OSF
HD:DAT
A
is the period of time the oscillator must be stopped in order for the OSF flag to be set over the voltage range of 1.3V
= -40°C to +85°C, unless otherwise noted.) (Note 8)
has only to be met if the device does not stretch the LOW period (t
2
C bus inactive, SCL = SDA = V
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
f
t
t
HIGH
T
LOW
C
WDS
BUF
OSF
SCL
t
t
R
F
SP
B
B
3 of 15
CC
R MAX +
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
CONDITIONS
.
t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
LOW
SU:DAT
0.1C
0.1C
0.1C
0.1C
MIN
20 +
20 +
20 +
20 +
100
100
250
100
100
4.7
4.0
4.7
4.0
4.7
4.7
1.3
0.6
1.3
0.6
0.6
0.6
) of the SCL signal.
0
0
0
B
B
B
B
≥ to 250ns must then be met. This is
B
B
B
B
IHMIN
TYP
30
of the SCL signal) in order to
MAX
1000
400
100
300
300
300
400
0.9
0.9
UNITS
kHz
ms
pF
μs
μs
μs
μs
μs
ns
μs
ns
ns
μs
ns
ns