DS28EC20 Maxim, DS28EC20 Datasheet
DS28EC20
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DS28EC20 Summary of contents
Page 1
... GENERAL DESCRIPTION The DS28EC20 is a 20480-bit, 1-Wire organized as 80 memory pages of 256 bits each. An additional page is set aside for control functions. Data is written to a 32-byte scratchpad, verified, and then copied to the EEPROM memory special feature, blocks of eight memory pages can be write protected or put in EPROM-Emulation mode, where bits can only be changed from state ...
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... Standard speed Overdrive speed Standard speed Overdrive speed Standard speed Overdrive speed Standard speed Overdrive speed Standard speed Overdrive speed DS28EC20: 20Kb 1-Wire EEPROM -0.5V, +6V 20mA -40°C to +85°C +150°C -55°C to +125°C +300C +250C +260C MIN TYP ...
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... Note 13: The earliest recognition of a negative edge is possible at t Note 14: Defines maximum possible bit rate. Equal to 1/(t Note 15: Interval after t during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS28EC20 present. Minimum RSTL limit maximum limit is t PDHMAX Note 16: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. ...
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... Standard speed (Notes 1, 14) Standard speed (Notes 1, 15) Standard speed (Notes 1, 15) Standard speed (Notes 1, 16) Standard speed (Notes 1, 16) (Note 17) (Note 18) At +25° +70°C (Notes 21, 22, 23 DS28EC20: 20Kb 1-Wire EEPROM MIN TYP MAX UNITS 0.3 2.2 k 2000 pF 0.05 3.5 µA ...
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... The earliest recognition of a negative edge is possible at t Note 13: Defines maximum possible bit rate. Equal to 1/(t Note 14: Interval after t during which a bus master is guaranteed to sample a logic 0 on I/O if there is a DS28EC20 present. Minimum RSTL limit maximum limit is t PDHMAX in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from V ...
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... Not Connected DESCRIPTION The DS28EC20 combines 20Kb of data EEPROM with a fully featured 1-Wire interface in a single chip. The memory is organized as 80 pages of 256 bits each. In addition, the device has one page for control functions such as permanent write protection and EPROM-Emulation mode for individual 2048-bit (8-page) memory blocks. A volatile 256-bit memory page called the scratchpad acts as a buffer when writing data to the EEPROM to ensure data integrity ...
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... For operation at overdrive speed, the DS28EC20 requires V 64-BIT ROM Each DS28EC20 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits. ...
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... EEPROM plus a memory block lock byte and a register page lock byte. Starting at address 0A20h, the DS28EC20 has a read-only memory page that stores a factory byte and a 2-byte field reserved for a factory- administered service to program manufacturer identification. All other bytes of that page are reserved. The manufacturer ID can be a customer-supplied identification code that assists the application software in identifying the product the DS28EC20 is associated with ...
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... Register Page Lock (See text) (55h no valid manufacturer ID, AAh Factory Byte 0A23h to 0A24h are a valid Manufacturer ID) Factory Trim Bytes (Unspecified value) Manufacturer ID Validity depends on factory byte Reserved (Unspecified value DS28EC20: 20Kb 1-Wire EEPROM PROTECTION CODES (NOTES) ...
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... CRC16, it should send the Read Scratchpad command to verify data integrity preamble to the scratchpad data, the DS28EC20 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not need to continue reading ...
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... The DS28EC20’s memory address range is 0000h to 0A3Fh. If the bus master sends a target address higher than this, the DS28EC20’s internal circuitry sets the four most significant address bits to zero as they are shifted into the internal address register. The Read Scratchpad command reveals the modified target address. The master identifies such address modifications by comparing the target address read back to the target address transmitted ...
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... Sending less than 16 bits for the target address sets the PF flag. pad Offset = (T[4:0]), Clears PF, AA the memory is write-protected, the DS28EC20 copies the data byte from the target address into the scratchpad. Master TX Data Byte If the memory is in EPROM mode, the To Scratchpad Offset ...
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... Master TX Reset ? N N Scrpad. Offset = 11111b ? Y Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as sent by the DS28EC20 N Master TX Reset ? DS28EC20: 20Kb 1-Wire EEPROM To Figure Part See note in Write Scratchpad flow chart for additional details. From Figure Part ...
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... RX “1”s TX Reset ? To Figure Part 55h N Pad ? Master Y * 1-Wire idle high for t for power PROG DS28EC20: 20Kb 1-Wire EEPROM To Figure Part Copy- Protected ? DS28EC20 copies Scratch- pad Data to Address DS28EC20 TX “0” ...
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... Master RX Byte from FFh Byte Memory Address Y Master TX Reset End of Page? Y Master RX CRC16 of Command, Address, Data st (1 Pass); CRC16 of Data (Subsequent Passes) CRC OK? N Master TX Reset DS28EC20: 20Kb 1-Wire EEPROM N Bus Master RX “1”s N Master TX Reset ? Y DS28EC20 Increments Address Counter N Y ...
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... Copy Scratchpad sequence. 1-Wire BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28EC20 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing) ...
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... All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28EC20 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ...
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... The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at overdrive speed allows the bus master to address a specific DS28EC20 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS28EC20 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function command ...
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... Match ROM Search ROM Command? Command DS28EC20 TX Bit 0 DS28EC20 TX Bit 0 Master TX Bit Bit 0 Bit 0 Match? Match? Y DS28EC20 TX Bit 1 DS28EC20 TX Bit 1 Master TX Bit Bit 1 Bit 1 Match? Match? Y DS28EC20 TX Bit 63 DS28EC20 TX Bit 63 Master TX Bit Bit 63 Bit 63 Match? Match? ...
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... To Figure 9, 1 Part From Figure Part Resume Command From Figure Part To Figure Part NOTE: For operation at overdrive speed, the DS28EC20 requires V A5h 3Ch N Overdrive Skip ROM Master TX Reset ? N Y Master TX Reset ? N 1) The OD flag remains the device was already at overdrive speed before the Overdrive Match ROM command was issued ...
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... Figure 10 shows the initialization sequence required to begin any communication with the DS28EC20. A reset pulse followed by a presence pulse indicates that the DS28EC20 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the ...
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... For a write-zero time slot, the voltage on the data line must stay below the V W1LMAX until the write-zero low time t W0LMIN should not exceed V during the entire t ILMAX DS28EC20 needs a recovery time t Figure 11. Read/Write Timing Diagram Write-One Time Slot t V W1L PUP ...
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... During the t RL line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS28EC20 does not hold the data line low at all, and the voltage starts rising as soon over. ...
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... CRC GENERATION The DS28EC20 uses two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS28EC20 to determine if the ROM data has been received error-free. ...
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... RST PD Select WS TA READ SCRATCHPAD RST PD Select RS TA-E/S COPY SCRATCHPAD (SUCCESS) RST PD Select CPS TA-E/S COPY SCRATCHPAD ( COPY PROTECTED) RST PD Select CPS TA-E/S DESCRIPTION Programming <Data to EOS> CRC16\ FF Loop <Data to EOS> CRC16\ FF Loop Programming AA Loop FF Loop DS28EC20: 20Kb 1-Wire EEPROM ...
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... RoHS status. PACKAGE TYPE 6 TSOC 3 TO-92 (bulk) 3 TO-92 (tape and reel) FF Loop <Data to EOP> CRC16\ <32 Bytes> PACKAGE CODE OUTLINE NO. D6+1 Q3+1 Q3 DS28EC20: 20Kb 1-Wire EEPROM CRC16\ Loop LAND PATTERN NO. 21-0382 90-0321 21-0248 — 21-0250 — ...
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... Maxim Integrated Products DESCRIPTION , and related notes IO L REC SLOT PROG Maxim is a registered trademark of Maxim Integrated Products, Inc. DS28EC20: 20Kb 1-Wire EEPROM PAGES CHANGED — 11, 17, 18, 20, 21 (±5%), PUP 2– ...