DS28E04-100 Maxim, DS28E04-100 Datasheet - Page 20

• Manufacturer Part Number: DS28E04-100
• Description: The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM chip with seven address inputs
• Manufacturer: Maxim

READ MEMORY [F0h]
The Read Memory command is the general function to read data from the DS28E04-100. After issuing the
command, the master must provide a 2-byte target address in the range of 0000h to 0225h. After these two bytes,
the master reads data beginning from the target address and may continue until address 0225h. If the master
continues reading, the result will be logic 1s. The device's internal TA1, TA2, E/S, and scratchpad contents are not
affected by a Read Memory command.
The hardware of the DS28E04-100 provides a means to accomplish error-free writing to the memory section. To
safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is
recommended to packetize data into data packets the size of one memory page each. Such a packet would
typically store a 16-bit CRC with each page of data to insure rapid, error-free data transfers that eliminate having to
read a page multiple times to determine if the received data is correct or not. (See Application Note 114 for the
recommended file structure.)
WRITE REGISTER [CCh]
The conditional search settings and the status/control register are volatile. They need to be loaded after every
power-up cycle with the Write Register command. After issuing the command, the master sends the 2-byte target
address, which should be a value between 0223h and 0225h. Next the master sends the byte to be written to the
addressed cell. If the address was valid, the byte is immediately written to its memory location. The master now
can either end the command by issuing a 1-Wire reset or send another byte for the next higher address. Once
memory address 0225h has been written, any subsequent data bytes will be ignored. The master has to send a
1-Wire reset to end the command. Since the Write Register flow does not include any error-checking for the new
register data, it is important to verify correct writing by reading the registers using the Read Memory command.
PIO ACCESS READ [F5h]
In contrast to reading the PIO logical state from address 0220h, this command reads the PIO logical status in an
endless loop. After 32 bytes of PIO pin status the DS28E04-100 inserts an inverted CRC16 into the data stream,
which allows the master to verify whether the data was received error-free. A PIO Access Read can be terminated
at any time with a 1-Wire Reset. The state of the POL pin does not affect this command.
The status of both PIO channels is sampled at the same time. The first sampling occurs during the last (most
significant) bit of the command code F5h. The first (least significant) bit of the PIO status byte is associated to P0,
and the next bit to P1. The other 6 bits of a PIO status byte do not have corresponding PIO pins; they always read
"1". While the master receives the last bit of the PIO status byte, the next sampling occurs and so on until the
master has received 32 PIO samples. Next the master receives the inverted CRC16 of the command byte and 32
PIO samples (first pass) or the CRC of 32 PIO samples (subsequent passes). While the last (most significant) bit of
the CRC is transmitted, the next PIO sampling takes place. The sampling occurs with a delay of t
rising edge of the MS bit of the previous byte, as shown in Figure 10. The value of "x" is approximately 0.2µs.
Figure 10. PIO Access Read Timing Diagram
Notes:
1
2
The "previous byte" could be the command code, the data byte resulting from the previous PIO sample, or the
MS byte of a CRC16.
The sample point timing also applies to the PIO Access Write and Pulse command, with the "previous byte"
being the write confirmation byte (AAh).
IO
Example - Sampled State = FEh
MS 2 bits of
previous byte
t
REH
+x
V
Sampling Point
TH
20 of 37
LS 2 bits of
data byte (FEh)
REH
+ x from the