DS2413 Maxim, DS2413 Datasheet - Page 15

• Manufacturer Part Number: DS2413
• Description: The DS2413 is a dual-channel programmable I/O 1-Wire® chip
• Manufacturer: Maxim

Master-to-Slave
For a write-one time slot, the voltage on the data line must have crossed the V
low time t
threshold until the write-zero low time t
data line should not exceed V
the DS2413 needs a recovery time t
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V
read low time t
line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When
responding with a 1, the DS2413 does not hold the data line low at all, and the voltage starts rising as soon as t
over.
The sum of t
the master sampling window (t
most reliable communication, t
later than t
sufficient recovery time t
applies only to a single DS2413 attached to a 1-Wire line. For multidevice configurations, t
extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs
active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line drivers can be
used.
IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS)
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and
topology of the network, reflections from end points and branch points can add up, or cancel each other to some
extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the
1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, consequently, result in a search ROM command
coming to a dead end or cause a device-specific function command to abort. For better performance in network
applications, the DS2413 uses a new 1-Wire front end, which makes it less sensitive to noise and also reduces the
magnitude of noise injected by the slave device itself.
The 1-Wire front end of the DS2413 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line
2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.
3) There is a hysteresis at the low-to-high switching threshold V
4) There is a time window specified by the rising edge hold-off time t
Devices that have the parameters t
Wire front end.
impedance than a digitally switched transistor, converting the high-frequency ringing known from traditional
devices into a smoother low-bandwidth transition. The slew-rate control is specified by the parameter t
which has different values for standard and Overdrive speed.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.
below V
they extend below V
appear late after crossing the V
taken as the beginning of a new time slot (Figure 13, Case C, t
W1LMAX
MSRMAX
TH
RL
- V
RL
+  (rise time) on one side and the internal timing generator of the DS2413 on the other side define
HY
is expired. For a write-zero time slot, the voltage on the data line must stay below the V
. After reading from the data line, the master must wait until t
is expired. During the t
, it will not be recognized (Figure 13, Case A). The hysteresis is effective at any 1-Wire speed.
TH
REC
- V
for the DS2413 to get ready for the next time slot. Note that t
ILMAX
MSRMIN
RL
HY
should be as short as permissible, and the master should read close to but no
threshold (Figure 13, Case B, t
during the entire t
FPD
TH
REC
to t
, V
threshold and extend beyond the t
before it is ready for the next time slot.
W0LMIN
MSRMAX
RL
HY
, and t
window, when responding with a 0, the DS2413 starts pulling the data
is expired. For the most reliable communication, the voltage on the
) in which the master must perform a read from the data line. For the
REH
W0L
specified in their electrical characteristics use the improved 1-
15 of 18
or t
W1L
window. After the V
TH
GL
GL
. If a negative glitch crosses V
 t
< t
REH
REH
REH
REH
during which glitches are ignored, even if
).
). Deep voltage droops or glitches that
window cannot be filtered out and are
TH
SLOT
TH
threshold before the write-one
threshold has been crossed,
is expired. This guarantees
REC
TH
REC
specified herein
but does not go
needs to be
TL
until the
RL
FPD
TH
is
,