STM6600 STMicroelectronics, STM6600 Datasheet - Page 12

• Manufacturer Part Number: STM6600
• Description: Smart push-button on/off controller with smart reset and power-on lockout
• Manufacturer: STMicroelectronics

Operation
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Operation
The STM6600-STM6601 simplified smart push-button on/off controller with Smart Reset
and power-on lockout enables and disables power for the application depending on push-
button states, signals from the processor, and battery voltage.
Power-on
Because most of the processors have outputs in high-Z state before initialization, an internal
pull-down resistor is connected to PS
12, 13, and 18).
To power up the device the push-button PB has to be pressed for at least t
V
below V
V
goes low), reset output RST is asserted for t
by the processor. During initialization, the processor sets the PS
On the STM6600 the PS
t
high) - see
maximum time allowed for the system to power up and initialize the circuits driving the
PS
deasserted immediately, thus turning off the system power. If t
push-button release, the PS
disables the power and prevents discharging the battery if the push-button is stuck or it is
held for an unreasonable period of time and the application is not responding (see
and 10). PB status, INT status and V
power-up is completed.
On the STM6601 the PS
the enable signal is deasserted - see
the maximum time allowed for the power switch and processor to perform the proper power-
on. If the PS
released immediately, thus turning off the system power. PB status, INT status and V
undervoltage detection are not monitored during the entire t
feature prevents the user from turning on the system when there is a faulty power switch or
an unresponsive microprocessor.
Push-button interrupt
If the device works under normal operation (i.e. PS
pressed for more than t
generated on the INT output. By connecting INT to the processor interrupt input (INT or
NMI) a safeguard routine can be performed and the power can be shut down by setting
PS
Forced power-down mode
The PS
and can deassert the enable signal - see
ON_BLANK
CC
TH+
HOLD
HOLD
has to be above V
(see
HOLD
TH+
input. If the PS
low - see
Figure
expiration, otherwise the enable signal is deasserted (EN goes low, EN goes
Figure
during the t
HOLD
output can be forced low anytime during normal operation by the processor
13). After t
signal is low at the end of the blanking period, the enable output is
7, 8, 9, and 10. The time up to push-button release represents the
Figure
TH+
DEBOUNCE
DEBOUNCE
HOLD
HOLD
HOLD
14.
for the whole t
HOLD
DEBOUNCE
signal is low at push-button release, the enable output is
Doc ID 15453 Rev 10
signal has to be set high before t
signal has to be set high prior to push-button release and
, the counter is reset and starts to count again when V
state is checked at its expiration. This safety feature
, a negative pulse with minimum t
CC
HOLD
Figure 11
the enable signal is asserted (EN goes high, EN
undervoltage detection are not monitored until
DEBOUNCE
Figure
input during startup (see
REC
and 12. In this case the t
14.
and then the startup routine is performed
HOLD
period. If the battery voltage drops
is high) and the push-button PB is
ON_BLANK
ON_BLANK
ON_BLANK
HOLD
INT
Figure
signal high.
STM6600 - STM6601
period. This failsafe
_
Min
ON_BLANK
expires prior to
expires, otherwise
DEBOUNCE
width is
7, 8, 9, 10, 11,
period is
Figure 8
CC
and
CC
™
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