ST7MC2R6 STMicroelectronics, ST7MC2R6 Datasheet - Page 30

• Manufacturer Part Number: ST7MC2R6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2R6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to
tails.
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
Figure 15. Reset Block Diagram
30/309
1
Note 1: See “Illegal Opcode Reset” on page 244. for more details on illegal opcode reset conditions.
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by
option byte)
RESET vector fetch
RESET
section 11.2.1 on page 244
Figure
14:
V
Figure
DD
R
ON
15:
for further de-
Filter
GENERATOR
PULSE
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 14. RESET Sequence Phases
6.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized (see
tection is asynchronous and therefore the MCU
can enter reset state even in Halt mode.
Active Phase
256 or 4096 CLOCK CYCLES
INTERNAL RESET
RESET
WATCHDOG RESET
ILLEGAL OPCODE RESET
LVD RESET
ON
weak pull-up resistor.
Figure
INTERNAL
RESET
16). This de-
VECTOR
h(RSTL)in
FETCH
1)
in