ST92150CV1Q-Auto STMicroelectronics, ST92150CV1Q-Auto Datasheet - Page 130

• Manufacturer Part Number: ST92150CV1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92150CV1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
CLOCK MANAGEMENT (Cont’d)
7.3.3 CPU Clock Prescaling
The system clock, INTCLK, which may be the out-
put of the PLL clock multiplier, CLOCK2, CLOCK2/
16 or CK_AF, drives a programmable prescaler
which generates the basic time base, CPUCLK,
for the instruction executer of the ST9 CPU core.
This allows the user to slow down program execu-
tion during non processor intensive routines, thus
reducing power dissipation.
The internal peripherals are not affected by the
CPUCLK prescaler and continue to operate at the
full INTCLK frequency. This is particularly useful
when little processing is being done and the pe-
ripherals are doing most of the work.
The prescaler divides the input clock by the value
programmed in the control bits PRS2,1,0 in the
MODER register. If the prescaler value is zero, no
prescaling takes place, thus CPUCLK has the
same period and phase as INTCLK. If the value is
different from 0, the prescaling is equal to the val-
ue plus one, ranging thus from two (PRS[2:0] = 1)
to eight (PRS[2:0] = 7).
The clock generated is shown in
will be noted that the prescaling of the clock does
not preserve the 50% duty cycle, since the high
level is stretched to replace the missing cycles.
This is analogous to the introduction of wait cycles
for access to external memory. When External
Memory Wait or Bus Request events occur, CPU-
CLK is stretched at the high level for the whole pe-
riod required by the function
Figure 62. CPU Clock Prescaling
n
130/430
9
CPUCLK
INTCLK
PRS VALUE
000
001
010
011
100
101
110
111
Figure
62, and it
VA00260
7.3.4 Peripheral Clock
The system clock, INTCLK, which may be the out-
put of the PLL clock multiplier, CLOCK2, CLOCK2/
16 or CK_AF, is also routed to all ST9 on-chip pe-
ripherals and acts as the central timebase for all
timing functions.
7.3.5 Low Power Modes
The user can select an automatic slowdown of
clock frequency during Wait for Interrupt opera-
tion, thus idling in low power mode while waiting
for an interrupt. In WFI operation the clock to the
CPU core is stopped, thus suspending program
execution, while the clock to the peripherals may
be programmed as described in the following par-
agraphs. Two examples of Low Power operation in
WFI are illustrated in
Providing that low power operation during Wait for
Interrupt is enabled (by setting the LPOWFI bit in
the CLKCTL Register), as soon as the CPU exe-
cutes the WFI instruction, the PLL is turned off and
the system clock will be forced to CLOCK2 divided
by 16, or to the external low frequency clock,
CK_AF, if this has been selected by setting
WFI_CKSEL, and providing CKAF_ST is set, thus
indicating that the external clock is selected and
actually present on the CK_AF pin.
If the external clock source is used, the crystal os-
cillator may be stopped by setting the XTSTOP bit,
providing that the CK_AF clock is present and se-
lected, indicated by CKAF_ST being set. In this
case, the crystal oscillator will be stopped auto-
matically on entering WFI if the WFI_CKSEL bit
has been set.
It should be noted that selecting a non-existent
CK_AF clock source is impossible, since such a
selection requires that the auxiliary clock source
be actually present and selected. In no event can
a non-existent clock source be selected inadvert-
ently.
It is up to the user program to switch back to a fast-
er clock on the occurrence of an interrupt, taking
care to respect the oscillator and PLL stabilization
delays, as appropriate.
It should be noted that any of the low power modes
may also be selected explicitly by the user pro-
gram even when not in Wait for Interrupt mode, by
setting the appropriate bits.
If the FREEN bit is set, the PLL is not stopped dur-
ing Low Power WFI, increasing power consump-
tion.
Figure 63
and
Figure
64.