ST7263BH2 STMicroelectronics, ST7263BH2 Datasheet - Page 93

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ST7263BH2

Manufacturer Part Number
ST7263BH2
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7263BH2

4, 8, 16 Or 32 Kbytes Program Memory
high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection
ST7263Bxx
Control register 2 (SCICR2)
Reset value: 0000 0000 (00h)
TIE
7
TCIE
7 TIE Transmitter interrupt enable.
6 TCIE Transmission complete interrupt enable
5 RIE Receiver interrupt enable.
4 ILIE Idle line interrupt enable.
3 TE Transmitter enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE=1 in the SCISR register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC=1 in the SCISR register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SCISR
register
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1 in the SCISR register.
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”)
Caution: The TDO pin is free for general purpose I/O only when the TE and
RIE
sends a preamble (idle line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission
starts.
Doc ID 7516 Rev 8
RE bits are both cleared (or if TE is never set).
ILIE
Read/write
TE
RE
On-chip peripherals
RWU
SBK
0
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