STM32F217ZG STMicroelectronics, STM32F217ZG Datasheet - Page 166

• Manufacturer Part Number: STM32F217ZG
• Description: High-performance ARM Cortex-M3 MCU with 1 Mbyte Flash, 120 MHz CPU, ART Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F217ZG

• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII

Revision history
166/168
Table 91.
20-Dec-2011
Date
Document revision history (continued)
Revision
6
Updated SDIO register addresses in
Updated
and STM32F2xx for LQFP144
design between STM32F10xx and STM32F2xx for LQFP100
Figure 1: Compatible board design between STM32F10xx and
STM32F2xx for LQFP64
board design between STM32F10xx and STM32F2xx for LQFP176
package.
Updated
Updated
Updated
(OTG_FS)
In
and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added
ETH _RMII_TX_EN alternate function to PG11. Added EVENTOUT in
the list of alternate functions for I/O pin/balls. Removed
OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate
functions.
In
I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3 for
PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA,
OTG_FS_SCL and OTG_FS_INTN alternate functions. Updated
peripherals corresponding to AF12.
Removed CEXT and ESR from
conditions.
Added maximum power consumption at T
and maximum current consumptions in Stop
Added CRYPTO, RNG, and HASH consumption in
Peripheral current
Updated md minimum value in
Added examples in
generation (SSCG)
Updated
characteristics.
Updated
Updated
SMI,
RMII, and
for
Updated maximum f
Section 5.3.25: FSMC
changed C
asynchronous timings and waveforms. Updated
Synchronous multiplexed PSRAM write
UpdatedTable 80: DCMI
Updated
10 × 10 × 0.6 mm mechanical
Table 5: STM32F21x pin and ball
Table 6: Alternate function
MII.
Doc ID 17050 Rev 6
Table 60: Dynamics characteristics: Ethernet MAC signals for
Table 59: Dynamics characteristics: Ethernet MAC signals for
Figure 3: Compatible board design between STM32F10xx
Section 2.2.3: Memory protection
Section 2.2.6: Embedded
Section 2.2.28: Universal serial bus on-the-go full-speed
Table 50: SPI characteristics
Figure 45: ULPI timing diagram
Table 87: UFBGA176+25 - ultra thin fine pitch ball grid array
Table 61: Dynamics characteristics: Ethernet MAC signals
L
to remove external FS OTG PHY support.
value to 30 pF, and modified FSMC configuration for
consumption.
Section 5.3.11: PLL spread spectrum clock
characteristics.
S
values in
characteristics: updated
characteristics.
package, and added
mapping: changed I2S3_SCK to
Changes
data.
package,
Table 32: SSCG parameters
Table 62: ADC
Table 10: General operating
SRAM.
definitions: changed SPI2_MCK
STM32F215xx, STM32F217xx
Figure 14: Memory
and
timings.
Figure 2: Compatible board
and
A
=25 °C in
Table 51: I2S
unit.
mode.
Table 57: ULPI
Figure 4: Compatible
characteristics.
Table 68 toTable
Figure 59:
Table 22:
Table 19: Typical
map.
constraint.
package,
timing.
79,