STM32F100RC STMicroelectronics, STM32F100RC Datasheet - Page 69

• Manufacturer Part Number: STM32F100RC
• Description: Mainstream Value line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 24 MHz CPU, motor control and CEC functions
• Manufacturer: STMicroelectronics

Specifications of STM32F100RC

• Peripherals Supported: timers, ADC, SPIs, I2Cs, USARTs and DACs
• Conversion Range: 0 to 3.6 V
• One 16-bit, 6-channel Advanced-control Timer: up to 6 channels for PWM output, dead time generation and emergency stop
• Systick Timer: 24-bit downcounter

STM32F100xC, STM32F100xD, STM32F100xE
5.3.14
Table 43.
1. FT = 5V tolerant. To sustain a voltage higher than V
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
Symbol
V
R
R
C
V
V
I
PMOS/NMOS contribution
lkg
hys
PU
PD
IH
IO
IL
Standard I/O input
low level voltage
I/O FT
level voltage
Standard I/O input
high level voltage
I/O FT
level voltage
Standard I/O Schmitt
trigger voltage
hysteresis
I/O FT Schmitt trigger
voltage hysteresis
Input leakage
current
Weak pull-up
equivalent resistor
Weak pull-down
equivalent resistor
I/O pin capacitance
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under the conditions summarized in
compliant.
I/O static characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
in
Parameter
(1)
(1)
Figure 25
(4)
input low
input high
(2)
to the series resistance is minimum
and
(2)
(5)
(5)
Figure 26
V
Standard I/Os
SS
Conditions
V
V
V
V
V
≤
DD
DD
I/O FT
IN
IN
IN
V
=
=
= 5 V
>
≤
IN
V
V
2 V
2 V
for 5 V tolerant I/Os.
≤
DD
SS
V
DD
Doc ID 15081 Rev 5
DD
+0.3 the internal pull-up/pull-down resistors must be disabled.
0.41*(V
0.42*(V
(~10% order)
5% V
DD
–0.3
–0.3
Min
200
DD
–2 V) +1.3 V
30
30
Figure 23
DD
–2)+1 V
Table
(3)
.
Table 43
9. All I/Os are CMOS and TTL
and
Typ
40
40
Figure 24
5
are derived from tests
0.32*(V
0.28*(V
Electrical characteristics
for standard I/Os, and
V
DD
DD
DD
Max
–2 V)+0.75 V
5.5
5.2
±1
50
50
–2 V)+0.8 V
3
+0.3
69/97
Unit
mV
mV
µA
kΩ
kΩ
pF
V