STM32F101VD STMicroelectronics, STM32F101VD Datasheet - Page 90

• Manufacturer Part Number: STM32F101VD
• Description: Mainstream Access line, ARM Cortex-M3 MCU with 384 Kbytes Flash, 36 MHz CPU
• Manufacturer: STMicroelectronics

Specifications of STM32F101VD

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, DAC, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

Electrical characteristics
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Table 54.
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
DuCy(SCK)
t
t
t
t
t
t
dis(SO)
t
w(SCKH)
v(SO)
t
w(SCKL)
v(MO)
su(NSS)
t
a(SO)
Symbol
1/t
t
the data.
the data in Hi-Z
t
t
h(NSS)
t
su(MI)
t
h(MO)
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(1)(2)
(1)(1)
(1)(1)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock duty
cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
Doc ID 14610 Rev 8
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
STM32F101xC, STM32F101xD, STM32F101xE
Conditions
PCLK
PCLK
= 20 MHz
= 36 MHz,
4t
2t
Min
PCLK
PCLK
30
15
50
5
5
5
4
2
2
0
3t
Max
PCLK
18
70
60
10
25
18
5
8
MHz
Unit
ns
ns
%