PSMN9R0-30YL NXP Semiconductors, PSMN9R0-30YL Datasheet

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

PSMN9R0-30YL

Manufacturer Part Number
PSMN9R0-30YL
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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PSMN9R0-30YL
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1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
Table 1.
Symbol
V
P
T
Dynamic characteristics
Q
Q
Avalanche ruggedness
E
I
Static characteristics
R
D
j
DS
tot
DS(AL)S
DSon
GD
G(tot)
PSMN9R0-30YL
N-channel 30 V 8 mΩ logic level MOSFET in LFPAK
Rev. 04 — 9 March 2011
High efficiency due to low switching
and conduction losses
Class-D amplifiers
DC-to-DC converters
Quick reference data
Parameter
drain-source voltage
drain current
total power
dissipation
junction temperature
drain-source on-state
resistance
gate-drain charge
total gate charge
non-repetitive
drain-source
avalanche energy
Conditions
T
T
see
T
V
T
V
V
see
V
V
V
I
R
D
j
mb
mb
j
GS
GS
DS
GS
DS
GS
GS
≥ 25 °C; T
= 25 °C
= 55 A; V
Figure
Figure 15
= 25 °C; V
= 25 °C; see
= 12 V; see
= 12 V; see
= 10 V; I
= 4.5 V; I
= 4.5 V; I
= 10 V; T
= 50 Ω; unclamped
1; see
sup
j
D
≤ 175 °C
D
D
j(init)
GS
= 15 A;
≤ 30 V;
= 10 A;
= 10 A;
Figure
Figure 14
Figure 2
= 10 V;
= 25 °C;
Figure 3
Suitable for logic level gate drive
sources
Motor control
Server power supplies
14;
Min
-
-
-
-55
-
-
-
-
Product data sheet
Typ
-
-
-
-
6.16 8
2.4
8.7
-
Max Unit
30
61
46
175
-
-
16
V
A
W
°C
mΩ
nC
nC
mJ

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PSMN9R0-30YL Summary of contents

Page 1

... PSMN9R0-30YL N-channel mΩ logic level MOSFET in LFPAK Rev. 04 — 9 March 2011 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. ...

Page 2

... T pulsed ° ° j(init) ≤ Ω; unclamped V sup GS All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL Graphic symbol mbb076 Min - ≤ 80 nJ; - DS(AL kΩ -20 Figure 1 - Figure 1 ...

Page 3

... T mb (°C) Fig 2. Limit DSon All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL 100 150 Normalized total power dissipation as a function of mounting base temperature 10 μs 100 μ ...

Page 4

... Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN9R0-30YL Product data sheet N-channel mΩ logic level MOSFET in LFPAK Conditions see Figure All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL Min Typ Max - 1.9 2.7 003aac544 δ ...

Page 5

... DS see Figure MHz °C; see Figure 0.5 Ω 4 4.7 Ω R G(ext) All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL Min Typ Max Unit 1.3 1.7 2. 2.45 V ...

Page 6

... V ( 2.8 2.6 2.4 2 (V) DS Fig 6. 003aac539 (A) D Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL Min Typ - 0. ( 150 ° ° Transfer characteristics: drain current as a function of gate-source voltage ...

Page 7

... GS Fig 10. Drain-source on-state resistance as a function 003aab271 typ max Fig 12. Gate-source threshold voltage as a function of All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL 12 R DSon (mΩ gate-source voltage; typical values 3 V ...

Page 8

... (V) DS 600 400 200 (nC) G Fig 16. Input, output and reverse transfer capacitances All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL GS(pl) V GS(th GS1 GS2 ...

Page 9

... PSMN9R0-30YL Product data sheet N-channel mΩ logic level MOSFET in LFPAK ( 150 ° 0.0 0.2 0.4 0.6 All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL 003aac536 25 °C 0.8 1.0 V (V) SD © NXP B.V. 2011. All rights reserved ...

Page 10

... A 0 2.5 scale max 4.41 2.2 0.9 0.25 0.30 4.10 4.20 3.62 2.0 0.7 0.19 0.24 3.80 REFERENCES JEDEC JEITA MO-235 All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL detail (1) (1) ( 5.0 3.3 6.2 0.85 1.3 1.27 4.8 3.1 5.8 0.40 0.8 EUROPEAN PROJECTION ...

Page 11

... Data sheet status Change notice Product data sheet - Product data sheet - Product data sheet - Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL Supersedes PSMN9R0-30YL v.3 PSMN9R0-30YL v.2 PSMN9R0-30YL v.1 - © NXP B.V. 2011. All rights reserved ...

Page 12

... In case an individual agreement is concluded only the terms and conditions of the respective All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL © NXP B.V. 2011. All rights reserved ...

Page 13

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 04 — 9 March 2011 PSMN9R0-30YL Trademarks © NXP B.V. 2011. All rights reserved ...

Page 14

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 9 March 2011 Document identifier: PSMN9R0-30YL ...

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