PUSB3F4-TBR NXP Semiconductors, PUSB3F4-TBR Datasheet
PUSB3F4-TBR
Related parts for PUSB3F4-TBR
PUSB3F4-TBR Summary of contents
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... PUSB3F4-TBR ESD protection for ultra high-speed interfaces Rev. 1 — 6 October 2011 1. Product profile 1.1 General description The device is designed to protect high-speed interfaces such as High-Definition Multimedia Interface (HDMI), DisplayPort, SuperSpeed USB, external Serial Advanced Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces against ElectroStatic Discharge (ESD) ...
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... Marking codes Limiting values Parameter input voltage electrostatic discharge voltage ambient temperature storage temperature All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR ESD protection for ultra high-speed interfaces Simplified outline Graphic symbol ...
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... MHz; capacitance difference V mutual channel MHz; capacitance V dynamic resistance positive transient channel V clamping voltage All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR ESD protection for ultra high-speed interfaces Min = 3 [1] 0.4 = 2.5 V bias [ ...
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... Sdd21 Normalized to 100 ; differential pairs CH1/CH2 versus CH3/CH4 Fig 2. Mixed-mode differential NEXT crosstalk; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR 018aaa003 (Hz) © NXP B.V. 2011. All rights reserved ...
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... Fig 4. 0 (pF) 0.2 (1) 0.0 (2) −0.2 −0.4 −0.5 1.5 3.5 = 2.5 V bias All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR 5 Gbit/s; USB 3.0 CP0 pattern Typical eye diagram for PUSB3F4-TBR 018aaa006 5.5 V (V) bias © NXP B.V. 2011. All rights reserved. 018aaa005 ...
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... PUSB3F4-TBR Product data sheet 018aaa008 2.0 2.5 I (A) Fig 7. 018aaa009 (A) Fig 9. All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR ESD protection for ultra high-speed interfaces 3 (V) 3.0 2.5 2.0 1.5 0.5 1.0 1.5 = 8/20 s; negative pulse IEC 61000-4- Dynamic resistance with negative clamping ...
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... When designing the Printed-Circuit Board (PCB), give careful consideration to basic high-speed routing guidelines, impedance matching, and signal coupling. Basic application diagram for the ESD protection of an HDMI interface is shown in Figure 10. Fig 10. Application diagram of HDMI ESD protection using PUSB3F4-TBR PUSB3F4-TBR Product data sheet ESD protection for ultra high-speed interfaces PUSB3F4-TBR ...
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... 2.6 1.1 0.40 0.45 2.5 1.0 0.5 2 0.35 0.40 2.4 0.9 0.2 0.30 0.35 References JEDEC JEITA - - - - - - All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR ESD protection for ultra high-speed interfaces detail 0.1 0.05 0.05 0.05 European projection SOT1176 sot1176-1_po Issue date ...
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... Stencil stencil of 75 2.45 1.5 With a stencil of 100 All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR ESD protection for ultra high-speed interfaces P 0. recommended. μ m gives an aspect ratio of 0.77 μ m one will obtain an aspect ratio of 0.58 μ SOT1176 ...
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... Human Body Model High-Definition Multimedia Interface Low Voltage Differential Signaling Near End Crosstalk Restriction of Hazardous Substances Transmission Line Pulse Transition Minimized Differential Signaling All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors 11. Revision history Table 7. Revision history Document ID Release date PUSB3F4-TBR v.1 20111006 PUSB3F4-TBR Product data sheet ESD protection for ultra high-speed interfaces Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR © NXP B.V. 2011. All rights reserved ...
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... NXP Semiconductors’ product specifications. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 1 — 6 October 2011 PUSB3F4-TBR © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 6 October 2011 Document identifier: PUSB3F4-TBR ...