PRTR5V0U2D NXP Semiconductors, PRTR5V0U2D Datasheet
PRTR5V0U2D
Available stocks
Related parts for PRTR5V0U2D
PRTR5V0U2D Summary of contents
Page 1
... The device is designed to protect two Hi-Speed data lines or high-frequency signal lines from the damage caused by ESD and other transients. PRTR5V0U2D integrates two ultra low capacitance rail-to-rail ESD protection channels and one additional ESD protection diode to ensure signal line protection even if no supply voltage is available ...
Page 2
... Measured from pin 5 to ground. 2. Pinning information Table 2. Pin Ordering information Table 3. Type number Package PRTR5V0U2D SC-74 4. Marking Table 4. Type number PRTR5V0U2D PRTR5V0U2D_1 Product data sheet Ultra low capacitance double rail-to-rail ESD protection Quick reference data Parameter input/output to ground capacitance input/output to input/output ...
Page 3
... Product data sheet Ultra low capacitance double rail-to-rail ESD protection Limiting values Parameter Conditions ambient temperature storage temperature ESD maximum ratings Parameter electrostatic discharge voltage Rev. 01 — 28 April 2009 PRTR5V0U2D Min 40 55 Conditions Min [1][2] IEC 61000-4-2 - (contact discharge) [2] MIL-STD-883 (human ...
Page 4
... Ultra low capacitance double rail-to-rail ESD protection ESD standards compliance I PP 100 % 0 ESD pulse waveform according to IEC 61000-4-2 Rev. 01 — 28 April 2009 PRTR5V0U2D Conditions > (contact) > 001aaa631 © NXP B.V. 2009. All rights reserved ...
Page 5
... C (I/O-I/O) (pF (V) (I/O-GND) Fig 3. Rev. 01 — 28 April 2009 PRTR5V0U2D Conditions Min Typ [ < [ MHz (I/O-GND) [ MHz; - 0.6 ...
Page 6
... ESD voltage waveform (IEC 61000-4-2 network) GND vertical scale = 200 V/div horizontal scale = 50 ns/div clamped 1 kV ESD voltage waveform (IEC 61000-4-2 network) Rev. 01 — 28 April 2009 PRTR5V0U2D 4 GHz DIGITAL OSCILLOSCOPE 10 ATTENUATOR 50 vertical scale = 10 V/div horizontal scale = 50 ns/div vertical scale = 10 V/div ...
Page 7
... Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended: 1. Place the PRTR5V0U2D as close to the input terminal or connector as possible. 2. The path length between the PRTR5V0U2D and the protected line should be minimized. ...
Page 8
... NXP Semiconductors 8. Package outline Fig 6. 9. Packing information Table 9. The indicated -xxx are the last three digits of the 12NC ordering code. Type number Package Description PRTR5V0U2D SOT457 [1] For further information and the availability of packing methods, see [2] T1: normal taping [3] T2: reverse taping ...
Page 9
... Ultra low capacitance double rail-to-rail ESD protection 3.45 1.95 0.95 2.825 0. 2.4 Reflow soldering footprint SOT457 (SC-74) 5.3 1. 2.85 Wave soldering footprint SOT457 (SC-74) Rev. 01 — 28 April 2009 PRTR5V0U2D 0.55 solder lands 0. solder resist solder paste occupied area Dimensions solder lands solder resist 0. occupied area Dimensions in mm ...
Page 10
... Table 10. Revision history Document ID Release date PRTR5V0U2D_1 20090428 PRTR5V0U2D_1 Product data sheet Ultra low capacitance double rail-to-rail ESD protection Data sheet status Change notice Product data sheet - Rev. 01 — 28 April 2009 PRTR5V0U2D Supersedes - © NXP B.V. 2009. All rights reserved ...
Page 11
... Export might require a prior authorization from national authorities. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 28 April 2009 PRTR5V0U2D © NXP B.V. 2009. All rights reserved ...
Page 12
... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PRTR5V0U2D All rights reserved. Date of release: 28 April 2009 Document identifier: PRTR5V0U2D_1 ...