ADP120 Analog Devices, ADP120 Datasheet - Page 5

• Manufacturer Part Number: ADP120
• Description: 100 mA, Low Quiescent Current, CMOS Linear Regulator
• Manufacturer: Analog Devices

ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP120 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
the device is dependent on the ambient temperature (T
power dissipation of the device (P
thermal resistance of the package (θ
Maximum junction temperature (T
ambient temperature (T
the formula
T
J
= T
A
+ (P
D
× θ
JA
)
A
) and power dissipation (P
J
is within the specified temperature
D
), and the junction-to-ambient
J
JA
) is calculated from the
).
Rating
−0.3 V to +6 V
−0.3 V to VIN
−0.3 V to +6 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
D
) using
A
), the
J
) of
Rev. B | Page 5 of 20
Junction-to-ambient thermal resistance (θ
is based on modeling and calculation using a four-layer board.
The junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
PCB material, layout, and environmental conditions. The speci-
fied values of θ
to JESD 51-7 and JESD 51-9 for detailed information regarding
board construction. For additional information, see Application
Note AN-617, MicroCSP
Ψ
with units of °C/W. Ψ
calculation using a four-layer board. JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as ther-
mal resistances. Ψ
through multiple thermal paths rather than a single path as in
thermal resistance, θ
convection from the top of the package as well as radiation
from the package, factors that make Ψ
world applications. Maximum junction temperature (T
calculated from the board temperature (T
dissipation (P
Refer to JESD51-8, JESD51-9, and JESD51-12 for more detailed
information about Ψ
THERMAL RESISTANCE
θ
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball, 0.4 mm Pitch WLCSP
ESD CAUTION
JA
JB
and Ψ
is the junction-to-board thermal characterization parameter
T
J
= T
JB
B
are specified for the worst-case conditions, that is, a
+ (P
D
) using the following formula:
JA
D
are based on a four-layer, 4” × 3” PCB. Refer
JB
× Ψ
measures the component power flowing
JB
JB
JB
JB
. Therefore, Ψ
.
)
of the package is based on modeling and
TM
Wafer Level Chip Scale Package.
JB
thermal paths include
JB
JA
θ
170
260
more useful in real-
may vary, depending on
JA
B
JA
) and power
) of the package
Ψ
43
58
JB
ADP120
J
) is
Unit
°C/W
°C/W