ADUC816 Analog Devices, ADUC816 Datasheet - Page 41

• Manufacturer Part Number: ADUC816
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC816

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

USER INTERFACE TO OTHER ON-CHIP ADuC816
PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC816 incorporates a 12-bit, voltage output DAC
on-chip. It has a rail-to-rail voltage output buffer capable of
DACCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
DACH/L
Function
SFR Address
Power-On Default Value
Bit Addressable
The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
REV. A
-
- -
Name
---
---
---
DACPIN
DAC8
DACRN
DACCLR
DACEN
-
- -
DAC Data Registers
DAC Data Registers, written by user to update the DAC output.
DACL (DAC Data Low Byte)
DACH (DAC Data High Byte) –>FCH
00H
No
DAC Control Register
No
Description
Reserved for Future Use.
Reserved for Future Use.
Reserved for Future Use.
DAC Output Pin Select.
DAC 8-bit Mode Bit.
DAC Output Range Bit.
DAC Clear Bit.
DAC Enable Bit.
FDH
00H
the 8 MSBs of the DAC and the 4 LSBs of the DAC are set to zero.
-
by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
by user to enable 8-bit DAC operation. In this mode the 8-bits in DACL SFR are routed to
by user to configure DAC range of 0 – AV
to “1” by user to enable normal DAC operation.
to “1” by user to enable normal DAC operation.
- -
Table XIV. DACCON SFR Bit Designations
by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
by user to operate the DAC in its normal 12-bit mode of operation.
by user to configure DAC range of 0 – 2.5 V.
to “0” by user to reset DAC data registers DACl/H to zero.
to “0” by user to power-down the DAC.
D
A
C
P
I
N
–>FBH
–>Both Registers
–>Both Registers
driving 10 kΩ/100 pF. It has two selectable ranges, 0 V to V
(the internal bandgap 2.5 V reference) and 0 V to AV
operate in 12-bit or 8-bit mode. The DAC has a control regis-
ter, DACCON, and two data registers, DACH/L. The DAC
output can be programmed to appear at Pin 3 or Pin 12. It
should be noted that in 12-bit mode, the DAC voltage output
will be updated as soon as the DACL data SFR has been writ-
ten; therefore, the DAC data registers should be updated as
DACH first followed by
D
A
C
8
DD
.
D
A
C
R
DACL.5
N
D
A
C
C
L
R
D
DD
A
C
. It can
E
N
REF