AD8574 Analog Devices, AD8574 Datasheet - Page 15

• Manufacturer Part Number: AD8574
• Description: Zero-Drift, Single-Supply, RRIO Quad Op Amp
• Manufacturer: Analog Devices

Specifications of AD8574

• -3db Bandwidth: 1.5MHz
• Slew Rate: 400mV/µs
• Vos: 1µV
• Ib: 10pA
• # Opamps Per Pkg: 4
• Input Noise (nv/rthz): 51nV/rtHz
• Vcc-vee: 2.7V to 6V
• Isy Per Amplifier: 975µA
• Packages: SOIC,SOP

AUTO-ZERO PHASE
In this phase, all ΦA
are open. Here, the nulling amplifier is taken out of the gain
loop by shorting its two inputs together. Of course, there is a
degree of offset voltage, shown as V
amplifier, that maintains a potential difference between the +IN
and −IN inputs. The nulling amplifier feedback loop is closed
through ΦA
amplifier and on C
Mathematically, this can be expressed in the time domain as
This can also be expressed as
The previous equations show that the offset voltage of the nulling
amplifier times a gain factor appears at the output of the nulling
amplifier and thus on the C
AMPLIFICATION PHASE
When the ΦB switches close and the ΦA
the amplification phase, the offset voltage remains on CM1 and
essentially corrects any error from the nulling amplifier. The
voltage across C
between the two inputs to the primary amplifier is designated as
V
can then be expressed as
Because ΦA
discharge, the voltage (V
the voltage at the output of the nulling amp (V
ΦA
frequency is designated as T
phases every 0.5 × T
and substituting Equation 4 and Equation 2 into Equation 3 yields
IN
, or V
X
V
V
is closed. If the period of the autocorrection switching
V
V
V
OA
OA
OA
OA
NA
[t] = A
[t] = A
IN
[ ]
[ ]
[ ]
t
t
t
= (V
2
X
=
=
=
, and V
is now open and there is no place for C
V
A
A
A
A
IN+
M1
NA
V
1
(V
A
A
V
V
OSA
+
is designated as V
IN
⎡
⎢
⎣
M1
− V
IN
OSA
t
OSA
[t] − V
X
B
S
[t] − B
, an internal capacitor in the AD857x.
. Therefore, in the amplification phase
[ ]
−
t
switches are closed, and all ΦB switches
A
IN−
[ ]
t
1
2
appears at the output of the nulling
+
NA
). The output of the nulling amplifier
T
) at the present time (t) is equal to
A
A
OSA
S
M1
V
S
⎤
⎥
⎦
A
, the amplifier switches between
V
OA
[t]) − B
capacitor.
OSA
[t]
[ ]
t
OSA
NA
A
−
V
, inherent in the nulling
. The potential difference
A
NA
X
A
[t]
switches open for
B
OA
A
V
) at the time when
1
OSA
+
⎡
⎢
⎣
B
t
A
M1
−
to
1
2
T
S
⎤
⎥
⎦
Rev. E | Page 15 of 24
(1)
(2)
(3)
(4)
(5)
For the sake of simplification, it can be assumed that the auto-
correction frequency is much faster than any potential change
in V
offset voltage are a function of temperature variation or long-
term wear time, both of which are much slower than the
auto-zero clock frequency of the AD857x, which effectively
makes the V
or
Here, the auto-zeroing becomes apparent. Note that the V
term is reduced by a factor of 1 + B
nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Therefore, the
primary amplifier output voltage is the voltage at the output of the
AD857x amplifier. It is equal to
In the amplification phase, V
Combining terms yield
The AD857x architecture is optimized in such a way that
A
A
simplified to
Most obvious is the gain product of both the primary and nulling
amplifiers. This A
high open-loop gain. To understand how V
the overall effective input offset voltage of the complete amplifier,
set up the generic amplifier equation of
where:
k is the open-loop gain of an amplifier.
V
Putting Equation 12 into the form of Equation 11 gives
A
A
OS, EFF
B
= A
B
OSA
V
V
V
V
V
V
V
V
V
A
is much greater than A
OA
OUT
OUT
OUT
OUT
OUT
OUT
OA
IN
B
is its effective offset voltage.
B
or V
V
, B
[ ]
[ ]
[ ]
[t] = A
t
[t] = V
[t] = V
IN
t
t
= k × (V
[ ]
[ ]
A
t
t
(
[ ]
A
=
t
= B
OSB
OS
=
=
=
B
A
+
. This is a good assumption because changes in
time invariant, and Equation 5 can be rewritten as
A
+
B
A
B
IN
IN
A
, and B
A
V
(V
A
A
[t]A
[t]A
B
B
⎛
⎜
⎜
⎝
IN
IN
V
A
V
A
IN
B
OSB
+ V
[ ]
term is what gives the AD857x its extremely
IN
[t] + V
t
B
A
A
)
B
B
[ ]
A
t
+
+
+
OS, EFF
A
A
AD8571/AD8572/AD8574
>> 1. In addition, the gain product to
+ A
+ V
B
A
+
A
B
1
OSB
A
A
B
1
B
)
OA
⎡
⎢
⎢
⎣
+
(
. Therefore, Equation 10 can be
A
OS, EFF
1
V
A
) + B
B
(V
+
V
B
OSA
= V
+
A
OSA
A
B
OSA
⎛
⎜
⎜
⎝
B
A
V
A
A
B
NB
A
+ V
IN
A
, which shows how the
V
⎞
⎟
⎟
⎠
+
B
)
1
, so this can be rewritten as
V
NB
[ ]
A
t
A
+
OSA
OSB
B
+
V
B
)
A
1
OSB
−
OSA
V
+
A
OSA
B
and V
A
A
B
A
⎞
⎟
⎟
⎠
V
⎤
⎥
⎥
⎦
OSA
OSB
relate to
OS
(10)
(11)
(12)
(13)
(6)
(7)
(8)
(9)