ADA4841-2 Analog Devices, ADA4841-2 Datasheet - Page 6

• Manufacturer Part Number: ADA4841-2
• Description: Dual Low Power, Low Noise and Distortion, Rail-to-Rail Output Amplifier
• Manufacturer: Analog Devices

Specifications of ADA4841-2

• -3db Bandwidth: 80MHz
• Slew Rate: 13V/µs
• Vos: 40µV
• Ib: 3µA
• # Opamps Per Pkg: 2
• Input Noise (nv/rthz): 2.1nV/rtHz
• Vcc-vee: 2.7V to 12V
• Isy Per Amplifier: 1.5mA
• Packages: SOIC,SOP

ADA4841-1/ADA4841-2
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature
Junction Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
specified for device soldered in circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type
8-lead SOIC_N
6-Lead SOT-23
8-lead MSOP
8-Lead LFCSP_WD
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4841-1/
ADA4841-2 is limited by the associated rise in junction
temperature (T
the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
amplifiers. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the die
due to the amplifier’s drive at the output. The quiescent power is
the voltage between the supply pins (V
current (I
JA
is specified for the worst-case conditions, that is, θ
S
).
J
) on the die. At approximately 150°C, which is
Rating
12.6 V
See Figure 5
−V
±1.8 V
−65°C to +125°C
−40°C to +125°C
JEDEC J-STD-20
150°C
θ
125
170
130
103
JA
S
S
D
) times the quiescent
) is the sum of the
− 0.5 V to +V
Unit
°C/W
°C/W
°C/W
°C/W
S
JA
+ 0.5 V
is
Rev. E | Page 6 of 20
RMS output voltages should be considered. If R
to −V
V
worst case, when V
In single-supply operation with R
is V
Airflow increases heat dissipation, effectively reducing θ
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θ
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC_N
(125°C/W), the 6-lead SOT-23 (170°C/W), 8-lead MSOP
(145°C/W), and 8-lead LFCSP_WD (103°C/W) on a JEDEC
standard 4-layer board. θ
ESD CAUTION
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
S
× I
OUT
P
P
P
S
OUT
D
D
D
, as in single-supply operation, the total drive power is
= V
2.0
1.5
1.0
0.5
= Quiescent Power + (Total Drive Power − Load Power)
=
=
. If the rms signal levels are indeterminate, consider the
0
–55
(
(
V
V
S
/2.
–45 –35 –25 –15 –5
S
S
×
×
I
I
S
S
)
)
+
+
OUT
⎛
⎜
⎜
⎝
(
V
V
2
= V
AMBIENT TEMPERATURE (°C)
S
R
S
4 /
L
×
JA
SOT-23
5
SOIC
)
S
V
2
values are approximations.
/4 for R
LFCSP
R
15 25 35 45 55 65 75 85 95 105 115
OUT
L
⎞
⎟
⎟
⎠
L
−
L
referenced to −V
V
to midsupply.
OUT
R
MSOP
L
2
L
is referenced
JA
S
, worst case
.
JA
125
.