AD7847 Analog Devices, AD7847 Datasheet - Page 7

• Manufacturer Part Number: AD7847
• Description: LC2MOS Complete, Dual 12-Bit MDAC, Parallel Loading Structure
• Manufacturer: Analog Devices

Specifications of AD7847

• Resolution (bits): 12bit
• Dac Update Rate: 250kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Par

CIRCUIT INFORMATION
D/A SECTION
A simplified circuit diagram for one of the D/A converters and
output amplifier is shown in Figure 10.
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
The output amplifier and feedback resistor perform the current
to voltage conversion giving
where D is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)
The output amplifier can maintain ± 10 V across a 2 kΩ load. It
is internally compensated and settles to 0.01% FSR (1/2 LSB)
in less than 5 µs. Note that on the AD7837, V
nected externally to R
INTERFACE LOGIC INFORMATION—AD7847
The input control logic for the AD7847 is shown in Figure 11.
The part contains a 12-bit latch for each DAC. It can be treated
as two independent DACs, each with its own CS input and a com-
mon WR input. CSA and WR control the loading of data to the
DAC A latch, while CSB and WR control the loading of the
DAC B latch. The latches are edge triggered so that input data
is latched to the respective latch on the rising edge of WR. If CSA
and CSB are both low and WR is taken high, the same data will
be latched to both DAC latches. The control logic truth table is
shown in Table I, while the write cycle timing diagram for the
part is shown in Figure 12.
V
REF
CSA
CSB
WR
2R
C
2R
B
SHOWN FOR ALL 1s ON DAC
2R
FB
A
V
R
.
OUT
2R
S9
R
= – D × V
2R
S8
R
REF
2R
S0
DAC A LATCH
DAC B LATCH
2R
OUT
R /2
must be con-
AGND
V
OUT
C C C C C SA
X
1
0
1
0
g
1
g
X = Don’t Care. g = Rising Edge Triggered.
INTERFACE LOGIC INFORMATION—AD7837
The input loading structure on the AD7837 is configured for
interfacing to microprocessors with an 8-bit-wide data bus. The
part contains two 12-bit latches per DAC—an input latch and
a DAC latch. Each input latch is further subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch. Only the
data held in the DAC latches determines the outputs from the part.
The input control logic for the AD7837 is shown in Figure 13,
while the write cycle timing diagram is shown in Figure 14.
LDAC
WR
CS
A0
A1
CSB
X
1
1
0
0
1
g
g
CSA, CSB
DATA
WR
Table I. AD7847 Truth Table
WR
1
X
g
g
g
0
0
0
t
1
DAC A MS
LATCH
INPUT
4
t
AD7837/AD7847
VALID
3
t
DATA
Function
No Data Transfer
No Data Transfer
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
LATCH
DAC A
4
12
DAC A LS
LATCH
t
INPUT
t
2
5
8
DB7 DB0
8
DAC B LS
LATCH
INPUT
4
LATCH
DAC B
12
DAC B LS
LATCH
INPUT
8