ADV7122 Analog Devices, ADV7122 Datasheet
ADV7122
Specifications of ADV7122
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ADV7122 Summary of contents
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... A single +5 V power supply, an external 1.23 V reference and pixel clock input is all that is required to make the part operational. The ADV7122 has additional video control signals, composite SYNC and BLANK. The ADV7121/ADV7122 is capable of generating RGB video ...
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ADV7121–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity, INL Differential Nonlinearity, DNL Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance, C ...
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... Typically 400 mW: 80 MHz Parts mW max Typically 350 mW: 50 MHz & 35 MHz Parts pV secs typ pV secs typ ns max Typically ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and –3– ADV7121/ADV7122 = 37 pF 560 L L SET unless otherwise noted.) *12 ...
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... ADV7121/ADV7122 TIMING CHARACTERISTICS Parameter 80 MHz Version fmax 12 NOTES 1 TTL input values are volts, with input rise/fall times outputs. See timing notes in Figure 1. 2 Temperature range ( +70 C. ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7121/ADV7122 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, p roper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... V (V)/IOG (mA) REF and the full-scale output current on IOR, IOG and IOB is given by: SET = 12,082 V (V)/R REF SET = 8,628 V (V)/ REF SET = 7,969 V (V)/ REF SET . AA and 5%). All V pins on the ADV7121/ADV7122 must be connected. AA –6– is connected to IOG) SYNC ( ) (SYNC being asserted) REV. B ...
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... BLANK and SYNC. All these digital inputs are specified to accept TTL logic levels. Clock Input The CLOCK input of the ADV7121/ADV7122 is typically the pixel clock rate of the system also known as the dot rate. The dot rate, and hence the required CLOCK frequency, will be ...
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... The required CLOCK frequency is thus 78.6 MHz. All video data and control inputs are latched into the ADV7121/ ADV7122 on the rising edge of CLOCK, as previously de- scribed in the “Digital Inputs” section recommended that the CLOCK input to the ADV7121/ADV7122 be driven by a TTL buffer (e.g., 74F244). V 92.5 IRE 7 ...
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... ADV7121: IOG* (mA) = 12,082 V (V)/R REF IOR, IOB (mA) = 8,628 V (V)/R REF IOR, IOG, IOB (mA) = 7,969 V *Only applies to the ADV7122 when SYNC is being used. If SYNC is not being encoded onto the green channel, then Equation 1 will be similar to Equation 2. ANALOG POWER PLANE + 5V 0.01 F COMP REF ...
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... This power plane should be connected to the regular PCB power plane (V point through a ferrite bead, as illustrated in Figure 8. This bead should be located within three inches of the ADV7121/ADV7122. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7121/ADV7122 power pins, voltage reference circuitry and any output amplifiers ...
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... For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 terminated 75 should be as close as possible to the ADV7121/ADV7122 minimize reflections. Additional information on PCB design is available in an appli- cation note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” ...
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... ADV7121/ADV7122 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Terminal Plastic Leaded Chip Carrier (P-44A) 40-Pin Plastic DIP (N-40A) –12– REV. B ...