AD768 Analog Devices, AD768 Datasheet - Page 10

• Manufacturer Part Number: AD768
• Description: 16-Bit, 30 MSPS D/A Converter
• Manufacturer: Analog Devices

Specifications of AD768

• Resolution (bits): 16bit
• Dac Update Rate: 30MSPS
• Dac Settling Time: 25ns
• Max Pos Supply (v): +5.25V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD768
APPLYING THE AD768
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configura-
tions for the AD768. While most figures take the output at
IOUTA, IOUTB can be interchanged in all cases. Unless other-
wise noted, it is assumed that I
set to nominal values.
For application that require the specified dc accuracies, proper
resistor selection is required. In addition to absolute resistor tol-
erances, resistor self-heating can result in unexpected errors. For
optimal INL, the buffered voltage output is recommended as
shown in Figure 23. In this configuration, self-heating of R
may cause a change in gain, producing a bow in the INL curve.
This effect can be minimized by selection of a low temperature
coefficient resistor.
UNBUFFERED VOLTAGE OUTPUT CONFIGURATIONS
Figure 21 shows the AD768 configured to provide a unipolar
output range of approximately 0 V to –1 V. The nominal full-
scale current of 20 mA flows through the parallel combination
of the 50
(from the R-2R ladder), for a combined 47.6 . This produces
an ideal full-scale voltage of –0.952 V with respect to LADCOM.
In addition, the 1 k DAC output resistance has a tolerance of
variation results in a gain error which can be easily compensated
for by adjusting I
In this configuration, it is important to note the restrictions from
the output compliance limits. The maximum negative voltage
compliance is –1.2 V, prohibiting use of a 100
a 0 V to –2 V output swing. One additional consideration for
operation in this mode is integral nonlinearity. As the voltage at
the output node changes, the finite output impedance of the
DAC current steering switches gives rise to small changes in the
output current that vary with output voltage, producing a bow
(up to 8 LSBs) in the INL. For optimal INL performance, the
buffered voltage output mode is recommended.
The INL is also slightly dependent on the termination of the
unused output (IOUTB) as described in the ANALOG OUT-
PUT section. To eliminate this effect, IOUTB should be termi-
nated with the same impedance as IOUTA, so both outputs see
the same resistive divider to ground. This will keep the current
in LADCOM constant, minimizing any code-dependent IR
drops within the DAC ladder that may give rise to additional
nonlinearities.
AC-Coupled Output
Configuring the output as shown in Figure 22 provides a bipolar
output signal from the AD768 without requiring the use of a
summing amplifier. The ac load impedance presented to the
20% which may vary the full-scale gain by 1%. This linear
Figure 21. 0 V to –1 V Unbuffered Voltage Output
R
L
resistor and the 1 k DAC output resistance
REFIN
AD768
LADCOM
IOUTA
IOUTB
.
28
27
1
REFIN
and full-scale currents are
R
49.9
R
49.9
L
L
VA
VB
load to produce
FB
–10–
DAC output is the parallel combination of the AD768’s output
impedance, R
with the values given in Figure 22 is 0.5 V assuming R
The gain of the circuit will be a function of the tolerances of the
impedances R
Choosing the value of R
desired –3 dB high pass cutoff frequency and the bias current,
I
quency can be approximated by the equation,
The dc offset of the output is a function of the bias current of
the subsequent stage and the value of R
C = 390 pF, R
is approximately 20.4 kHz and the dc offset would be 20 mV.
BUFFERED VOLTAGE OUTPUT CONFIGURATIONS
Unipolar Configuration
For positive output voltages, or voltage ranges greater than
allowed by output compliance limits, some type of external
buffer is needed. A wide variety of amplifiers may be selected
based on considerations such as speed, accuracy and cost. The
AD9631 is an excellent choice when dynamic performance is
important, offering low distortion up to 10 MHz. Figure 23
shows the implementation of 0 V to +2 V full-scale unipolar
buffered voltage output. The amplifier establishes a summing
node at ground for the DAC output. The buffered output volt-
age results from the DAC output current flowing through the
amplifier’s feedback resistor, R
scale current across R
range of 0 V through +2 V. The same configuration using a pre-
cision amplifier such as the AD845 is recommended for optimal
dc linearity.
Buffered Output Using a Current Divider
The configuration shown in Figure 23 may not be possible in
cases where the amplifier cannot supply the requisite 20 mA
feedback current. As an alternative, Figure 24 shows amplifier
A1 in conjunction with a resistive current divider. The values of
R
supplied by A1. Current, I
tor, R
ceed 60
B
Figure 22. 0.5 V to –0.5 V Unbuffered AC-Coupled Output
Figure 23. Unipolar 0 V to +2 V Buffered Voltage Output
FF
, of the subsequent stage connected to R
and R
L
. The parallel combination of R
L
to avoid exceeding the specified compliance voltage.
are chosen to limit the current, I
f
L
–3 dB
LAD
, and bias resistor R
B
AD768
= 20 k , and I
LADCOM
AD768
, R
= 1/[2
LADCOM
IOUTA
IOUTB
IOUTA
B
IOUTB
, and R
FB
B
(100 ) produces an output voltage
27
28
1
and C will depend primarily on the
27
28
1
2
, is shunted to ground through resis-
L
.
(R
R
49.9
FB
B
L
= 1.0 A, the –3 dB frequency
. In this case, the 20 mA full-
B
B
+ R
. The nominal output swing
R
49.9
A1
100
L
R
L
FF
B
C
FB
R
. For example, if
and R
LAD
B
. The –3 dB fre-
3
)
R
, which must be
B
I
B
L
C].
should not ex-
B
REV. B
>> R
L
.