AD7564 Analog Devices, AD7564 Datasheet - Page 13

• Manufacturer Part Number: AD7564
• Description: +3.3 V/+5 V, Low Power, Quad 12-Bit CMOS DAC
• Manufacturer: Analog Devices

Specifications of AD7564

• Resolution (bits): 12bit
• Dac Update Rate: 1.8MSPS
• Dac Settling Time: 550ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser

MICROPROCESSOR INTERFACING
AD7564 to 80C51 Interface
A serial interface between the AD7564 and the 80C51 micro-
controller is shown in Figure 21. TXD of the 80C51 drives
SCLK of the AD7564 while RXD drives the serial data line of
the part. The FSIN signal is derived from the port line P3.3.
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the data word transmitted to the AD7564 corresponds to the
loading sequence shown in Table I. When data is to be trans-
mitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of TXD. The 80C51 transmits its serial data in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. To load data to the AD7564, P3.3 is left low
after the first eight bits are transferred and a second byte of data
is then transferred serially to the AD7564. When the second
serial transfer is complete, the P3.3 line is taken high. Note that
the 80C51 outputs the serial data byte in a format which has the
LSB first. The AD7564 expects the MSB first. The 80C51
transmit routine should take this into account.
LDAC and CLR on the AD7564 are also controlled by 80C51
port outputs. The user can bring LDAC low after every two
bytes have been transmitted to update the DAC which has been
programmed. Alternatively, it is possible to wait until all the in-
put registers have been loaded (sixteen byte transmits) and then
update the DAC outputs.
REV.
B
*ADDITIONAL PINS OMMITTED FOR CLARITY
80C51*
Figure 21. AD7564 to 80C51 Interface
P3.5
RXD
P3.4
P3.3
TXD
LDAC
FSIN
CLR
SCLK
SDIN
AD7564*
–13–
AD7564 to 68HC11 Interface
Figure 22 shows a serial interface between the AD7564 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7564 while the MOSI output drives the serial data line of
the AD7564. The FSIN signal is derived from a port line
(PC7 shown).
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes (MSB first), with only eight falling clock
edges occurring in the transmit cycle. To load data to the
AD7564 , PC7 is left low after the first eight bits are transferred
and a second byte of data is then transferred serially to the
AD7564. When the second serial transfer is complete, the PC7
line is taken high.
In Figure 22, LDAC and CLR are controlled by the PC6
and PC5 port outputs. As with the 80C51, each DAC of the
AD7564 can be updated after each two-byte transfer, or else
all DACs can be simultaneously updated. This interface
is suitable for both 3 V and 5 V versions of the 68HC11
microcontroller.
*ADDITIONAL PINS OMMITTED FOR CLARITY
64HC11*
Figure 22. AD7564 to 64HC11 Interface
MOSI
SCK
PC5
PC6
PC7
CLR
LDAC
FSIN
SDIN
SCLK
AD7564*
AD7564
3