AD7835 Analog Devices, AD7835 Datasheet - Page 9

• Manufacturer Part Number: AD7835
• Description: LC2MOS Quad 14-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD7835

• Resolution (bits): 14bit
• Dac Update Rate: 100kSPS
• Dac Settling Time: 10µs
• Max Pos Supply (v): +15.75V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Byte,Par

Table 8. AD7835 Pin Function Descriptions
Pin No.
MQFP
1, 5, 33, 34,
37, 41, 44
2
3, 4, 31, 30
8, 7, 6
9
10
11
12
13
14
15
NC = NO CONNECT
BYSHF
V
V
DSGA
LDAC
OUT
OUT
CLR
NC
NC
A2
A1
A0
1
2
10
11
Pin No. PLCC
3, 6, 7, 11, 39,
40, 43
15
16
17
18
19
20
21
8
9, 10, 37, 36
14, 13, 12
1
2
3
4
5
6
7
8
9
Figure 7. AD7835 MQFP Pin Configuration
44
12 13 14 15 16 17 18 19 20 21 22
PIN 1
IDENTIFIER
43
42
41
(Not to Scale)
TOP VIEW
Pin Mnemonic
NC
DSGA
V
A0, A1, A2
CLR
LDAC
BYSHF
CS
WR
V
DGND
40 39 38
AD7835
OUT
CC
1 to V
37
OUT
4
36 35 34
Description
No Connect.
Device Sense Ground A Input. Used in conjunction with the CLR input for power-on
protection of the DACs. When CLR is low, DAC outputs V
potential on the DSGA pin.
DAC Outputs.
Address Inputs. A0 and A1 are decoded to select one of the four input latches for a data
transfer. A2 is used to select all four DACs simultaneously.
Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low,
all analog outputs are switched to the externally set potentials on the DSG pins (V
and V
signal outputs remain at the DSG potentials until LDAC is brought low. When LDAC is
brought low, the analog outputs are switched back to reflect their individual DAC output
levels. As long as CLR remains low, the LDAC signals are ignored, and the signal outputs
remain switched to the potential on the DSG pins.
Load DAC Input (Level Sensitive). This input signal, in conjunction with the WR and CS
input signals, determines how the analog outputs are updated. If LDAC is maintained
high while new data is being loaded into the device’s input registers, no change occurs
on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four
input registers are transferred into their respective DAC latches, updating the analog
outputs simultaneously. Alternatively, if LDAC is brought low while new data is being
entered, the addressed DAC latch and corresponding analog output are updated
immediately on the rising edge of WR.
Byte Shift Input. When low, it shifts the data on DB0 to DB7 into the DB8 to DB13 half of
the input register.
Level-Triggered Chip Select Input (Active Low). The device is selected when this input is
low.
Level-Triggered Write Input (Active Low). When active, it is used in conjunction with CS
to write data over the input databus.
Logic Power Supply: 5 V ± 5%.
Digital Ground.
33
32
30
29
28
27
26
25
24
23
31
NC
DSGB
V
V
DB13
DB12
DB11
DB10
DB9
DB8
DB7
OUT
OUT
OUT
2 follow DSGA, and V
3
4
Rev. D | Page 9 of 28
NC = NO CONNECT
OUT
BYSHF
V
V
DSGA
LDAC
3 and V
OUT
OUT
CLR
NC
NC
A2
A1
A0
1
2
12
15
17
10
11
13
14
16
7
8
9
Figure 8. AD7835 PLCC Pin Configuration
OUT
18 19 20 21 22 23 24 25 26 27 28
6
4 follow DSGB). When CLR is brought high, the
5
4
3
(Not to Scale)
TOP VIEW
2
AD7835
OUT
1
1 and V
PIN 1
IDENTIFIER
44
AD7834/AD7835
43
OUT
42 41 40
2 are forced to the
39
38
37
36
35
34
33
32
31
30
29
NC
DSGB
V
V
DB13
DB12
DB11
DB10
DB9
DB8
DB7
OUT
OUT
OUT
3
4
1