AD9748 Analog Devices, AD9748 Datasheet
AD9748
Specifications of AD9748
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AD9748 Summary of contents
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... The AD9748 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9748’s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced with a slight degradation in performance by lowering the full-scale current output ...
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... DAC Transfer Function ............................................................. 12 Analog Outputs........................................................................... 12 Digital Inputs .............................................................................. 13 Clock Input.................................................................................. 13 DAC Timing................................................................................ 14 Power Dissipation....................................................................... 14 Applying the AD9748 ................................................................ 15 Differential Coupling Using a Transformer............................... 15 Differential Coupling Using an Op Amp................................ 16 Single-Ended, Unbuffered Voltage Output............................. 16 Single-Ended, Buffered Voltage Output Configuration........ 16 Power and Grounding Considerations, Power Supply Rejection...................................................................................... 17 Evaluation Board ...
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... V 100 nA 1. kΩ 0.5 MHz 0 ppm of FSR/°C ±50 ppm of FSR/°C ±100 ppm of FSR/°C ±50 ppm/°C 3.3 3.6 V 3.3 3.6 V 3.3 3 135 145 mW 145 FSR/V +0. FSR/V +85 °C = 100 MSPS, and MHz. OUT AD9748 ...
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... AD9748 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLOCK 1 Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% to 90%) ...
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... Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode. DB0–DB7 CLOCK IOUTA OR IOUTB = 20 mA, unless otherwise noted. OUTFS Min Typ 2 −10 −10 5 2.0 1.5 1.5 0 0.75 1.5 0.5 1 LPW 0.1% 0.1% Figure 2. Timing Diagram Rev Page AD9748 Max Unit V 0.9 V +10 μA +10 μ 2. ...
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... AD9748 ABSOLUTE MAXIMUM RATINGS Table 4. With Respect to Parameter Min AVDD ACOM −0.3 DVDD DCOM −0.3 CLKVDD CLKCOM −0.3 ACOM DCOM −0.3 ACOM CLKCOM −0.3 DCOM CLKCOM −0.3 AVDD DVDD −3.9 AVDD CLKVDD −3.9 DVDD CLKVDD −3.9 CLK+, CLK−, SLEEP DCOM − ...
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... Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated if not used. DB1 ADJ PIN 1 (LSB) DB0 2 23 REFIO INDICATOR DVDD 3 22 ACOM AD9748 IOUTA IOUTB TOP VIEW ACOM (Not to Scale AVDD AVDD CONNECT Figure 3. Pin Configuration Rev Page AD9748 ...
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... It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone For offset MIN MAX 3.3V AVDD ACOM 150pF AD9748 CURRENT SOURCE ARRAY IOUTA SEGMENTED LSB IOUTB SWITCHES SWITCHES MODE ...
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... THD@165MSPS 75 70 THD@50MSPS 65 60 THD@100MSPS 55 SINAD@165MSPS 50 SINAD@50MSPS SINAD@100MSPS 45 SINAD@210MSPS (MHz) OUT Figure 9. SINAD/THD vs. f (Differential Output) OUT 25MSPS CLOCK f = 7.81MHz OUT SFDR = 65.0dBc AMPLITUDE = 0dBFS FREQUENCY (MHz) AD9748 THD@50MSPS THD@100MSPS THD@165MSPS THD@210MSPS 100 THD@210MSPS 100 10 12 ...
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... SFDR = 56.2dBc AMPLITUDE = 0dBFS Figure 14. Single-Tone Spectral Plot @ 210 MSPS (Single-Ended Output) 3.3V AVDD 150pF 1.2V REF AD9748 CURRENT SOURCE ARRAY SEGMENTED LSB SWITCHES SWITCHES LATCHES DIGITAL DATA INPUTS (DB7–DB0) Figure 15. Simplified Block Diagram Rev Page 5ns/DIV Figure 13. Step Response (Single-Ended Output) ...
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... REFIO minimizes any loading of the external reference. , sets the reference REFIO REFERENCE CONTROL AMPLIFIER The AD9748 contains a control amplifier that is used to regulate the full-scale output current, I configured as a V-I converter, as shown in Figure 17, so that its current output external resistor, R ...
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... Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the AD9748 to provide the required power and voltage levels to different loads. Rev Page and V REF = {(2 × ...
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... The negative output compliance range of − set by the breakdown limits of the CMOS process. Operation beyond this maximum limit can result in a breakdown of the output stage and affect the reliability of the AD9748. The positive output compliance range is slightly dependent on the full-scale output current, I ...
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... SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω AVDD. This digital input also contains an active pull-down circuit that ensures that the AD9748 remains enabled if this input is left disconnected. The AD9748 takes less than power down and approximately 5 μs to power back up. POWER DISSIPATION ...
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... ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (that is, V swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9748. A differential resistor can be inserted in applications where DIFF the output of the transformer is connected to the load, R via a passive reconstruction filter or cable ...
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... In this case, AVDD, which is the positive analog supply for both the AD9748 and the op amp, is also used to level shift the differential output of the AD9748 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... OUTFS is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise occurs over the spectrum from tens of kilohertz to several megahertz. The PSRR vs. frequency of the AD9748 AVDD supply over this frequency range is shown in Figure 30 ...
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... AD9748 easily and effectively in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9748 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination ...
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... DB8X 14 13 DB7X 16 15 DB6X 18 17 DB5X 20 19 DB4X 22 21 DB3X 24 23 DB2X 26 25 DB1X 28 27 DB0X JP3 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT AD9748 CKEXTX ...
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... CVDD 12 21 CLK IA CLK 13 20 CLKB IB CLKB 14 19 CCOM ACOM1 15 18 CMODE AVDD 16 CMODE 17 MODE AVDD1 AD9748LFCSP TP7 R30 10Ω WHT CVDD JP1 MODE CLKB JP2 CKEXT CLK AVDD C17 0.1μF SLEEP TP11 WHT R29 10kΩ DB8 DB9 DB10 DB11 ...
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... Figure 35. Evaluation Board Layout—Primary Side Figure 36. Evaluation Board Layout—Secondary Side Rev Page AD9748 ...
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... AD9748 Figure 37. Evaluation Board Layout—Ground Plane Figure 38. Evaluation Board Layout—Power Plane Rev Page ...
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... Figure 39. Evaluation Board Layout Assembly—Primary Side Figure 40. Evaluation Board Layout Assembly—Secondary Side Rev Page AD9748 ...
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... AD9748ACPRL7 −40°C to +85°C 1 AD9748ACPZ −40°C to +85°C 1 AD9748ACPZRL7 −40°C to +85°C AD9748ACP-PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...