AD5391 Analog Devices, AD5391 Datasheet - Page 23

• Manufacturer Part Number: AD5391
• Description: 16-Channel 12-Bit 3V/5V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5391

• Resolution (bits): 12bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

DATA DECODING
AD5390/AD5392
The AD5390/AD5392 contain an internal 14-bit data bus.
The input data is decoded depending on the data loaded to
the REG1 and REG0 bits of the input serial register. This is
shown in Table 10.
Data from the serial input register is loaded into the addressed
DAC input register, offset (c) register, or gain (m) register. The
format data, and the offset (c) and gain (m) register contents
are shown in Table 11 to Table 13.
Table 10. Register Selection
REG1
1
1
0
0
Table 11. AD5390/AD5392 DAC Data Format
(REG1 = 1, REG0 = 1)
DB13 to DB0
11 1111
11 1111
10 0000
10 0000
01 1111
00 0000
00 0000
Table 12. AD5390/AD5392 Offset Data Format
(REG1 = 1, REG0 = 0)
DB13 to DB0
111111
111111
100000
100000
011111
000000
000000
Table 13. AD5390/AD5392 Gain Data Format
(REG1 = 0, REG0 = 1)
DB13 to DB0
11 1111
10 1111
01 1111
00 1111
00 0000
REG0
1
0
1
0
1111
1111
0000
0000
1111
0000
0000
1111
1111
0000
0000
1111
0000
0000
1111
1111
1111
1111
0000
Register Selected
Input data register (x1)
Offset register (c)
Gain register (m)
Special function registers (SFRs)
1111
1110
0001
0000
1111
0001
0000
1110
1110
1110
1110
0000
1111
1110
0001
0000
1111
0001
0000
DAC Output (V)
2 V
2 V
2 V
2 V
2 V
2 V
0
Offset (LSB)
+8191
+8190
+1
+0
–1
–8191
–8192
Gain Factor
1
0.75
0.5
0.25
0
REF
REF
REF
REF
REF
REF
× (16383/16384)
× (16382/16384)
× (8193/16384)
× (8192/16384)
× (8191/16384)
× (1/16384)
Rev. C | Page 23 of 40
AD5391
The AD5391 contains an internal 12-bit data bus. The input
data is decoded depending on the value loaded to the REG1 and
REG0 bits of the input serial register. The input data from the
serial input register is loaded into the addressed DAC input
register, offset (c) register, or gain (m) register. The format data
and the offset (c) and gain (m) register contents are shown in
Table 14 to Table 16.
Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)
DB11 to DB0
1111
1111
1000
1000
0111
0000
0000
Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)
DB11 to DB0
1111
1111
1000
1000
0111
0000
0000
Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)
DB11 to DB0
1111
1011
0111
0011
0000
1111
1111
0000
0000
1111
0000
0000
1111
1111
0000
0000
1111
0000
0000
1111
1111
1111
1111
0000
AD5390/AD5391/AD5392
1110
1110
1110
1110
0000
1111
1110
0001
0000
1111
1110
0001
0000
1111
0001
0000
1111
0001
0000
DAC Output (V)
2 V
2 V
2 V
2 V
2 V
2 V
0
Offset (LSB)
+2047
+2046
+1
+0
–1
–2047
–2048
Gain Factor
1
0.75
0.5
0.25
0
REF
REF
REF
REF
REF
REF
× (4095/4096)
× (4094/4096)
× (2049/4096)
× (2048/4096)
× (2047/4096)
× (1/4096)