AD5370 Analog Devices, AD5370 Datasheet - Page 16

• Manufacturer Part Number: AD5370
• Description: 40-Channel, 16-Bit, Serial Input, Voltage-Output DACs
• Manufacturer: Analog Devices

Specifications of AD5370

• Resolution (bits): 16bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5370
A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or X1B input register,
depending on the setting of the A /B bit in the Control register.
If the A /B bit is 0, data is written to the X1A register. If the A /B
bit is 1, data is written to the X1B register. Note that this single
bit is a global control and affects every DAC channel in the
device. It is not possible to set up the device on a per-channel
basis so that some writes are to X1A registers and some writes
are to X1B registers.
Each DAC channel also has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the X1A register is operated on
by a digital multiplier and an adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.
Although Figure 19 indicates a multiplier and an adder for each
channel, there is only one multiplier and one adder in the device,
and they are shared among all channels. This has implications
for the update speed when several channels are updated at once,
as described in the Register Update Rates section.
Each time data is written to the X1A register, or to the M or C
register with the A /B control bit set to 0, the X2A data is recal-
culated and the X2A register is automatically updated. Similarly,
X2B is updated each time data is written to X1B or to M or C
with A /B set to 1. The X2A and X2B registers are not readable
or directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A /B select register associated with each group of
eight DACs. If a bit in this register is 0, the DAC takes its data
from the X2A register; if 1, the DAC takes its data from the X2B
register (Bit 0 through Bit 7 control DAC0 to DAC7).
Note that, because there are 40 bits in five registers, it is possible
to set up, on a per-channel basis, whether each DAC takes its
data from the X2A or X2B register. A global command is also
provided, which sets all bits in the A /B select registers to 0 or to 1.
REGISTER
REGISTER
REGISTER
REGISTER
Figure 19. Data Registers Associated with Each DAC Channel
X1A
X1B
M
C
MUX
REGISTER
REGISTER
X2A
X2B
MUX
REGISTER
DAC
DAC
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LOAD DAC
All DAC channels in the AD5370 can be updated simultane-
ously by taking LDAC low when each DAC register is updated
from either its X2A or X2B register, depending on the setting of
the A /B select registers. The DAC register is not readable or
directly writable by the user.
OFFSET DAC CHANNELS
In addition to the gain and offset trim for each DAC channel,
there are two 14-bit offset DAC channels, one for Group 0 and
one for Group 1 to Group 4. These allow the output range of all
DAC channels connected to them to be offset within a defined
range. Thus, subject to the limitations of headroom, it is possible to
set the output range of Group 0 or Group 1 to Group 4 to be
unipolar positive, unipolar negative, or bipolar, either symmetrical
or asymmetrical about 0 V. The DAC channels in the AD5370
are factory trimmed with the offset DAC channels set at their
default values. This results in optimum offset and gain performance
for the default output range and span.
When the output range is adjusted by changing the value of the
offset DAC channel, an extra offset is introduced due to the
gain error of the offset DAC channel. The amount of offset is
dependent on the magnitude of the reference and how much
the offset DAC channel deviates from its default value. This
offset is quoted in the Specifications section.
The worst-case offset occurs when the offset DAC channel is at
positive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can be
removed by programming the channel’s C register with an
appropriate value. The extra offset caused by the offset DAC s
only needs to be taken into account when an offset DAC
channel is changed from its default value.
Figure 20 shows the allowable code range that can be loaded to
the offset DAC channel; this is dependent on the reference value
used. Thus, for a 5 V reference, the offset DAC channel should
not be programmed with a value greater than 8192 (0x2000).
5
4
3
2
1
0
0
Figure 20. Offset DAC Code Range
4096
OFFSET DAC CODE
8192
12288
RESERVED
16383