AD5724R Analog Devices, AD5724R Datasheet
AD5724R
Specifications of AD5724R
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AD5724R Summary of contents
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... The parts offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, 10 μs typical settling time, and an on-chip +2.5 V reference. The AD5724R/AD5734R/AD5754R use a serial interface that operates at clock rates MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs ...
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... Layout Guidelines....................................................................... 31 Galvanically Isolated Interface ................................................. 31 Microprocessor Interfacing....................................................... 31 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 3/09—Rev Rev. A Added AD5724R Model ............................................... Throughout Added 12-Bit Resolution .............................................. Throughout Changes to Resolution and Integral Nonlinearity (INL) Parameters (Table 2)..........................................................................4 Changes to Endnote 2 (Table 2) ......................................................5 Added Endnote 4 (Table 4) ..............................................................6 Added Figure 8 and Figure 11 ...................................................... 11 Added Figure 39 ...
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... FUNCTIONAL BLOCK DIAGRAM AD5724R/AD5734R/AD5754R DV CC SDIN SCLK SYNC SDO CLR BIN/2sCOMP AD5724R 12-BIT AD5734R 14-BIT AD5754R 16-BIT 2.5V REFERENCE n INPUT DAC REGISTER A REGISTER A INPUT SHIFT REGISTER AND CONTROL INPUT DAC LOGIC REGISTER B REGISTER B INPUT DAC REGISTER C REGISTER C INPUT DAC REGISTER D ...
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... T LOAD LOAD Table 2. Parameter ACCURACY Resolution AD5754R AD5734R AD5724R Total Unadjusted Error (TUE) 2 Integral Nonlinearity (INL) AD5754R AD5734R AD5724R Differential Nonlinearity (DNL) Bipolar Zero Error 3 Bipolar Zero TC Zero-Scale Error 3 Zero-Scale TC Offset Error Offset Error TC 3 Gain Error 3 Gain Error 3 ...
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... CC 1 For specified performance, headroom requirement is 0 INL is the relative accuracy measured from Code 512, Code 128, Code 32 for the AD5754R, AD5734R, AD5724R respectively. 3 Guaranteed by characterization; not production tested. 4 The on-chip reference is production trimmed and tested at 25°C and 85° characterized from −40°C to +85°C. ...
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... AD5724R/AD5734R/AD5754R AC PERFORMANCE CHARACTERISTICS 4 16 −4 200 pF, all specifications LOAD MIN Table 3. 2 Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Crosstalk DAC-to-DAC Crosstalk Digital Feedthrough Output Noise 0 ...
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... INPUT WORD FOR DAC N INPUT WORD FOR DAC N DB23 UNDEFINED INPUT WORD FOR DAC N Figure 3. Daisy-Chain Timing Diagram Rev Page AD5724R/AD5734R/AD5754R DB0 ...
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... AD5724R/AD5734R/AD5754R SCLK 1 SYNC SDIN INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED Figure 4. Readback Timing Diagram Rev Page NOP CONDITION SELECTED REGISTER DATA ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION max – T )/θ Rev Page AD5724R/AD5734R/AD5754R ...
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... It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance OUT OUT OUT AD5724R/ AD5734R SIG_GND OUT AD5754R SIG_GND BIN/2sCOMP 20 5 TOP VIEW DAC_GND (Not to Scale) DAC_GND SYNC 7 ...
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... AV /AV = +6.5V/0V, RANGE = + 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 500 1000 1500 2000 2500 CODE Figure 8. AD5724R Integral Nonlinearity Error vs. Code 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 50,000 60,000 Figure 9. AD5754R Differential Nonlinearity Error vs. Code 0.15 0.10 0.05 –0.05 –0.10 –0.15 –0.20 Figure 10. AD5734R Differential Nonlinearity Error vs. Code ...
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... AD5724R/AD5734R/AD5754R –2 –4 –6 –8 –40 – TEMPERATURE (°C) Figure 12. AD5754R Integral Nonlinearity Error vs. Temperature 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –40 – TEMPERATURE (°C) Figure 13. AD5754R Differential Nonlinearity Error vs. Temperature –2 –4 –6 – ...
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... Figure 23. Digital Current vs. Logic Input Voltage Rev Page AD5724R/AD5734R/AD5754R ±5V RANGE ±10V RANGE – TEMPERATURE (°C) Figure 21. Bipolar Zero Error vs. Temperature ±5V ±10V +10V – TEMPERATURE (° ...
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... AD5724R/AD5734R/AD5754R 0.010 ±5V RANGE, CODE = 0xFFFF ±10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF +5V RANGE, CODE = 0xFFFF 0.005 ±5V RANGE, CODE = 0x0000 ±10V RANGE, CODE = 0x0000 0 –0.005 –0.010 –0.015 –0.020 –25 –20 –15 –10 –5 0 OUTPUT CURRENT (mA) Figure 24 ...
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... LINE 73.8V CH1 1 CH1 LINE 73.8V Figure 34. REFOUT Output Noise (100 kHz Bandwidth) = ±16. CH1 Figure 35. REFOUT Output Noise (0 Bandwidth) Rev Page AD5724R/AD5734R/AD5754R 5V CH2 500mV M 200µs CH1 2.9V Figure 33. REFOUT Turn-On Transient 10µ LINE 1µ LINE 1.2V 1.2V ...
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... /AV = ±6.5V, RANGE = ± /AV = +6.5V/0V, RANGE = + 500 1000 1500 2000 2500 3000 CODE Figure 39. AD5724R Total Unadjusted Error vs. Code 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 TEMPERATURE COEFFICIENT (ppm/°C) Figure 40. Reference Output TC (−40°C to +85° ...
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... TEMPERATURE (°C) Figure 42. Reference Output Voltage vs. Temperature (−40°C to+ 85°C) 2.50120 2.50100 2.50080 2.50060 2.50040 2.50020 2.50000 2.49980 Figure 43. Reference Output Voltage vs. Temperature (0°C to 85°C) Rev Page AD5724R/AD5734R/AD5754R 20 DEVICES SHOWN TEMPERATURE (°C) 80 ...
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... This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724R/ AD5734R/AD5754R are monotonic over their full operating temperature range. Bipolar Zero Error ...
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... LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. AD5724R/AD5734R/AD5754R Voltage Reference TC Voltage reference measure of the change in the reference output voltage with a change in temperature. The reference TC ...
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... V to ±16 addition, the parts have software-selectable output ranges +10 V, +10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the AD5724R/AD5734R/ AD5754R in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy chaining or readback ...
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... Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5724R/AD5734R/AD5754R devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register ...
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... TRANSFER FUNCTION Table 8 to Table 16 show the relationships of the ideal input code to output voltage for the AD5754R, AD5734R, and AD5724R for all output voltage ranges. For unipolar output ranges, the data coding is straight binary. For bipolar output ranges, the data coding is user selectable via the BIN/ 2sCOMP pin and can be either offset binary or twos complement ...
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... REFIN × (1/65,536) 0000 0000 0000 0000 0 V AD5724R/AD5734R/AD5754R Analog Output ±10 V Output Range +4 × REFIN × (32,767/32,768) +4 × REFIN × (32,766/32,768) … +4 × REFIN × (1/32,768 −4 × REFIN × (1/32,768) … ...
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... AD5724R/AD5734R/AD5754R Ideal Output Voltage to Input Code Relationship—AD5734R Table 11. Bipolar Output, Offset Binary Coding Digital Input MSB LSB 11 1111 1111 1111 11 1111 1111 1110 … … … … 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 … … … … ...
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... Ideal Output Voltage to Input Code Relationship—AD5724R Table 14. Bipolar Output, Offset Binary Coding Digital Input MSB LSB ±5 V Output Range 1111 1111 1111 +2 × REFIN × (2047/2048) 1111 1111 1110 +2 × REFIN × (2046/2048) … … … … 1000 0000 0001 +2 × ...
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... AD5724R/AD5734R/AD5754R INPUT REGISTER The input register is 24 bits wide and consists of a read/write bit ( reserved bit (zero) which must always be set to 0, three register select bits (REG1, REG2, REG3), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin ...
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... The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel which the data transfer is to take place (see Table 18). The data bits are in positions DB15 to DB0 for the AD5754R (see Table 19), DB15 to DB2 for the AD5734R (see Table 20), and DB15 to DB4 for the AD5724R (see Table 21). Table 19. Programming the AD5754R DAC Register ...
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... AD5724R/AD5734R/AD5754R CONTROL REGISTER The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the control function selected. The control register options are shown in Table 24 and Table 25. Table 24. Programming the Control Register MSB ...
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... The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5724R/AD5734R/AD5754R. The power control register options are shown in Table 27 and Table 28. Table 27. Programming the Power Control Register ...
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... PU reference voltage is accessible at the REFIN/REFOUT pin for use as a reference source for other devices within the system. If the internal reference used external to the AD5724R/ AD5734R/AD5754R, it must first be buffered. Rev Page bit in the power ...
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... DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5724R/ AD5734R/AD5754R require a 24-bit data-word with data valid on the falling edge of SCLK. ...
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... SEATING 0.05 BSC PLANE 0.10 COPLANARITY Figure 51. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] ORDERING GUIDE 1 Model Resolution AD5724RBREZ 12 AD5724RBREZ-REEL7 12 AD5734RBREZ 14 AD5734RBREZ-REEL7 14 AD5754RBREZ 16 AD5754RBREZ-REEL7 16 EVAL-AD5754REBZ RoHS Compliant Part. ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...