AD7701 Analog Devices, AD7701 Datasheet - Page 14

• Manufacturer Part Number: AD7701
• Description: 16-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7701

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 16kSPS
• Interface: Ser
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 2.5V,Uni 2.5V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

AD7701
SLEEP MODE
The low power standby mode is initiated by taking the SLEEP
input low, which shuts down all analog and digital circuits and
reduces power consumption to 10 µW. The calibration coeffi-
cients are still retained in memory, but as the converter has been
quiescent, it is necessary to wait for the filter settling time (507,904
cycles) before accessing the output data.
DIGITAL INTERFACE
The AD7701’s serial communications port allows easy inter-
facing to industry-standard microprocessors. Three different
modes of operations are available, optimized for different types
of interface.
INTERNAL
SDATA (O)
DRDY (O)
SCLK (O)
STATUS
10V
CS (I)
1V
Figure 17. Single-Supply Operation
10k
10k
AD707
HI-Z
HI-Z
72 CLKIN CYCLES
REF
ANALOG SETTLING
64 CLKIN CYCLES
Figure 18. Timing Diagram for SSC Data Transmission Mode
0.1µF
0.1µF
AGND
V
DGND
MSB
AV
REF
AV
AD7701
SS
DD
DV
DV
DIGITAL COMPUTATION
SS
CS POLLED
DD
0.1µF
64 CLKIN CYCLES
0.1µF
–14–
1024 CLKIN CYCLES
Synchronous Self-Clocking Mode (SSC)
The SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
communication. This mode allows interfacing to 74XX299
universal shift registers without any additional decoding. The
SSC mode can also be used with microprocessors such as the
68HC11 and 68HC05, which allow an external device to clock
their serial port.
Figure 18 shows the timing diagram for SSC mode. Data is
clocked out by an internally generated serial clock. The AD7701
divides each sampling interval into 16 distinct periods. Eight
periods of 64 clock pulses are for analog settling and eight peri-
ods of 64 clock pulses are for digital computation. The status of
CS is polled at the beginning of each digital computation period. If
it is low at any of these times, SCLK will become active and the
data-word currently in the output register will be transmitted,
MSB first. After the LSB has been transmitted, DRDY goes
high and SDATA goes three-state. If CS, having been brought
low, is taken high again at any time during data transmission,
SDATA and SCLK will go three-state after the current bit
finishes. If CS is subsequently brought low, transmission will
resume with the next bit during the subsequent digital computa-
tion period. If transmission has not been initiated and completed
by the time the next data-word is available, DRDY will go high
for four clock cycles then low again as the new word is loaded
into the output register.
A more detailed diagram of the data transmission in the SSC
mode is shown in Figure 19. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK.
LSB
HI-Z
HI-Z
DIGITAL COMPUTATION
REV. E