AD7851 Analog Devices, AD7851 Datasheet - Page 19

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

POWER-DOWN OPTIONS
The AD7851 provides flexible power management to allow the
user to achieve the best power performance for a given throughput
rate. The power management options are selected by programming
the power management bits, PMGT1 and PMGT0, in the con-
trol register and by use of the SLEEP pin. Table VI summarizes
the power-down options that are available and how they can be
selected by using either software, hardware, or a combination of
both. The AD7851 can be fully or partially powered down. When
fully powered down, all the on-chip circuitry is powered down
and I
the on-chip circuitry except the reference is powered down and I
is 400 µA typ. The choice of full or partial power-down does not
give any significant improvement in throughput with a power-down
between conversions. (This is discussed in the Power-Up Times
section which follows.) But a partial power-down does allow the
on-chip reference to be used externally even though the rest of the
AD7851 circuitry is powered down. It also allows the AD7851 to
be powered up faster after a long power-down period when using
the on-chip reference. (See the Using the Internal (On-Chip) Ref-
erence section which follows.)
REV. B
DD
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
is 1 µA typ. If a partial power-down is selected, then all
0.91
AV
100mV pk-pk SINEWAVE ON AV
REF
DD
13.4
Figure 22. PSRR vs. Frequency
IN
0V TO V
= DV
= 4.098 EXT REFERENCE
ANALOG
AUTO POWER-
DOWN AFTER
CONVERSION
AUTO CAL ON
POWER-UP
INPUT
DD
25.7
(5V)
REF
= 5.0V
INPUT FREQUENCY (kHz)
UNIPOLAR RANGE
38.3
REFERENCE
CURRENT, I = 12mA TYP
EXTERNAL
OPTIONAL
0.01 F
0.1 F
50.3
DV
DD
DD
63.5
470nF
0.01 F
10 F
REF198
74.8
AIN(+)
AIN(–)
AMODE
C
POLARITY
AGND
DGND
C
SLEEP
CAL
Figure 23. Typical Low Power Circuit
REF2
REF1
0.01 F
87.4
AV
AD7851
REF
DD
100
IN
/REF
DV
0.1 F
DD
OUT
DD
CONVST
–19–
0.1 F
CLKIN
SYNC
DOUT
SCLK
INTERNAL
REFERENCE
SM1
SM2
DIN
When using the SLEEP pin, the power management bits
PMGT1 and PMGT0 should be set to 0 (default status on
power-up). Bringing the SLEEP pin logic high ensures normal
operation, and the part does not power down at any stage. This
may be necessary if the part is being used at high throughput
rates when it is not possible to power down between conver-
sions. If the user wishes to power down between conversions at
lower throughput rates (that is, <100 kSPS for the AD7851) to
achieve better power performances, then the SLEEP pin should
be tied logic low.
If the power-down options are to be selected in software only,
then the SLEEP pin should be tied logic high. By setting the
power management bits PMGT1 and PMGT0 as shown in
Table VI, a full power-down, full power-up, full power-down
between conversions, and a partial power-down between con-
versions can be selected.
A combination of hardware and software selection can also be
used to achieve the desired effect.
PMGT1
Bit
0
0
0
1
1
SW = Software selection, HW = Hardware selection.
SERIAL CLOCK OUTPUT
SERIAL DATA OUTPUT
MASTER
CLOCK
INPUT
OSCILLATOR
6MHz/7MHz
PMGT0
Bit
0
0
1
0
1
Table VI. Power Management Options
SERIAL MODE
SELECTION BITS
285kHz/ 333kHz PULSE
CONVERSION
START INPUT
SLEEP
Pin
0
1
X
X
X
GENERATOR
DIN AT DGND
=> NO WRITING
3-WIRE MODE
SELECTED
TO DEVICE
Comment
Full power-down between
conversions (HW/SW)
Full power-up (HW/SW)
Full power-down between
conversions (SW)
Full power-down (SW)
Partial power-down between
conversions (SW)
LOW POWER
C/ P
AD7851