AD7671 Analog Devices, AD7671 Datasheet
AD7671
Specifications of AD7671
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AD7671 Summary of contents
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... CMOS process and is available in a 48-lead LQFP and a tiny 48-lead LFCSP, with operation specified from –40∞C to +85∞C. PRODUCT HIGHLIGHTS 1. Fast Throughput The AD7671 is a very high speed (1 MSPS in Warp Mode and 800 kSPS in Normal Mode), charge redistribution, 16-bit SAR ADC. 2. Single-Supply Operation ...
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... AD7671–SPECIFICATIONS Parameter RESOLUTION ANALOG INPUT Voltage Range Common-Mode Input Voltage Analog Input CMRR Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise ...
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... INGND Symbol –3– AD7671 Typ Max 5 5.25 5 5.25 4 5. 112 125 7 +85 Input INA(R) Impedance REF 1.63 kW 948 W REF 711 W REF 948 W INGND 711 W INGND V Note 3 ...
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... AD7671 TIMING SPECIFICATIONS (continued) Parameter Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Refer to Figures 17 and 18 (Master Serial Interface Modes) ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD7671 Pin No. Mnemonic Type Description 1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 44– Connect. 4 BYTESWAP Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. ...
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... also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7671. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed ...
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... A measure of the acquisition performance measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7671 to achieve its rated accuracy after a full-scale step function is applied to its input. –8– – 1.76)/6.02) ...
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... TPC 2. Differential Nonlinearity vs. Code 0.3 0.6 0.9 1.2 1.5 1.8 POSITIVE INL – LSB TPC 3. Typical Positive INL Distribution (314 Units) REV. B Typical Performance Characteristics–AD7671 49152 65536 –3.0 TPC 4. Typical Negative INL Distribution (314 Units) 8000 7000 6000 5000 4000 3000 ...
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... AD7671 1MSPS f –20 SNR = 89.45dB THD = –100.05dB –40 SFDR = 100.49dB SINAD = 89.1dB –60 –80 –100 –120 –140 –160 –180 0 100 200 300 FREQUENCY – kHz TPC 7. FFT Plot 100 95 SNR 90 SINAD 100 FREQUENCY – kHz TPC 8. SNR, S/(N + D), and ENOB vs. Frequency ...
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... It is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. The AD7671 can be operated from a single 5 V supply and be interfaced to either digital logic housed in a 48-lead LQFP package or a 48-lead LFCSP package that com- bines space savings and flexible configurations as either serial or parallel interface ...
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... Transfer Functions Using the OB/2C digital input, the AD7671 offers two output codings: straight binary and twos complement. The ideal transfer characteristic for the AD7671 is shown in Figure 4 and Table III. 111...111 111...110 111...101 000...010 000 ...
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... Values with REF = 2.5 V. With REF = 3 V, all values will scale linearly. 2 This is also the code for an overrange analog input. 3 This is also the code for an underrange analog input. TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7671. Different circuitry shown on this diagram is optional and is discussed below. ANALOG SUPPLY (5V ADR421 2 ...
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... Figure 7. Analog Input CMRR vs. Frequency Except when using the 2.5 V analog input voltage range, R1 the AD7671 has to be driven by a very low impedance source to C avoid gain errors. That can be done by using a driver amplifier S whose choice is eased by the primarily resistive analog input circuitry of the AD7671 ...
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... AD7671. Power Supply The AD7671 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2 ...
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... Figure 10. This feature makes the AD7671 ideal for very low power battery applications. This does not take into account the power, if any, dissipated by ...
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... The serial interface is multiplexed on the parallel data bus. The AD7671 digital interface also accommodates both logic by simply connecting the OVDD supply pin of the AD7671 to the host system interface digital supply. Finally, by using the OB/2C input pin, straight binary and twos complement coding can be used ...
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... BUSY width. While the AD7671 is performing a bit decision important that voltage transients not occur on digital input/output pins or degra- dation of the conversion result could occur. This is particularly ...
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... Another advantage able to read the data at any speed MHz, which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7671 provides a “daisy-chain” feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired as, for instance, in isolated multiconverter applications ...
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... INVSCLK Figure 22. Interfacing the AD7671 to SPI Interface ADSP-21065L in Master Serial Interface As shown in Figure 23, the AD7671 can be interfaced to the ADSP-21065L using the serial interface in Master Mode without any glue logic required. This mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion at maximum speed transfer (DIVSCLK[0:1] both low) ...
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... Digital and analog ground planes should be joined in only one place, preferably underneath the AD7671, or, at least, as close as possible to the AD7671. If the AD7671 system where multiple devices require analog- to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7671 ...
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... AD7671 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 CCW 7.00 BSC SQ PIN 1 INDICATOR TOP VIEW 1.00 12 MAX 0.90 0.80 0.20 REF SEATING PLANE OUTLINE DIMENSIONS 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0.45 1 SEATING 10 PLANE 6 0.20 2 0.09 VIEW 0.10 MAX 0.50 COPLANARITY BSC VIEW A COMPLIANT TO JEDEC STANDARDS MS-026BBC ...
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... Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Edits to Table Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to TPC New TPC Addition of TPC Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to Driver Amplifier Choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 New Voltage Reference Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 New ST-48 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REV. B –23– AD7671 Page ...
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