AD7453 Analog Devices, AD7453 Datasheet - Page 13

• Manufacturer Part Number: AD7453
• Description: Pseudo Differential, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7453

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 555kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOT

When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 20 shows a graph of the THD versus analog input signal
frequency for different source impedances.
Figure 21 shows a graph of THD versus analog input frequency
for various supply voltages while sampling at 555 kSPS with an
SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
DIGITAL INPUTS
The digital inputs applied to the AD7453 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied, i.e., CS and SCLK, can go to 7 V and are
not restricted by the V
The main advantage of the inputs not being restricted to the
V
avoided. If CS or SCLK are applied before V
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V were applied prior to V
Figure 20. THD vs. Analog Input Frequency for Various Source Impedances
DD
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
+ 0.3 V limit is that power supply sequencing issues are
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–50
–55
–60
–65
–70
–75
–80
–85
–90
0
10
10
T
A
= 25°C
DD
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
+ 0.3 V limits as on the analog input.
V
DD
= 4.75V
100Ω
V
DD
V
DD
= 3.6V
10Ω
100
DD
100
= 2.7V
DD
.
, there is no risk
V
DD
62Ω
200Ω
= 5.25V
277
277
Rev. B | Page 13 of 20
REFERENCE
An external source is required to supply the reference to the
AD7453. This reference input can range from 100 mV to V
The specified reference is 2.5 V for the 2.7 V to 5.25 V power
supply range. The reference input chosen for an application
should never be greater than the power supply. Errors in the
reference source result in gain errors in the AD7453 transfer
function. A capacitor of at least 0.1 µF should be placed on the
V
AD780 and the ADR421. Figure 22 shows a typical connection
diagram for the V
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram of the serial interface
of the AD7453. The serial clock provides the conversion clock
and controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames the
data transfer. The falling edge of CS puts the track-and-hold
into hold mode and takes the bus out of three-state. The analog
input is sampled and the conversion is initiated at this point.
The conversion requires 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown at Point B in Figure 2. On the 16th SCLK falling edge, the
SDATA line goes back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion is terminated and the SDATA line goes back into
three-state.
The conversion result from the AD7453 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7453 consists of four leading zeros, followed by 12 bits of
conversion data, provided MSB first. The output coding is
straight (natural) binary.
*ADDITIONAL PINS OMITTED FOR CLARITY
V
DD
REF
0.1µF
pin. Suitable reference sources for the AD7453 include the
Figure 22. Typical V
10nF
0.1µF
REF
pin.
NC
REF
1
2
3
4
Connection Diagram for V
NC = NO CONNECT
V
TEMP
GND
IN
AD780
OPSEL
TRIM
V
OUT
8
7
6
5
2.5V
NC
NC
NC
DD
AD7453*
= 5 V
AD7453
0.1µF
V
DD
V
REF
DD
.