AD7680 Analog Devices, AD7680 Datasheet - Page 15

• Manufacturer Part Number: AD7680
• Manufacturer: Analog Devices

Specifications of AD7680

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

SDATA
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered
down between each conversion, or a series of conversions may
be performed at a high throughput rate, and then the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7680 is in
power-down, all analog circuitry is powered down.
To enter power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the 10th falling edge of SCLK
as shown in
window of SCLKs, the part enters power-down, the conversion
that was initiated by the falling edge of CS is terminated, and
SDATA goes back into three-state. If CS is brought high before
the second SCLK falling edge, the part remains in normal mode
and will not power down. This avoids accidental power-down
due to glitches on the CS line.
SCLK
CS
Figure 17
1
THE PART BEGINS
TO POWER UP
. Once
SDATA
SCLK
CS
CS has been brought high in this
INVALID DATA
10
1
t
POWER UP
2
Figure 17. Entering Power-Down Mode
Figure 18. Exiting Power-Down Mode
20
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In order to exit this mode of operation and power up the
AD7680 again, a dummy conversion is performed. On the
falling edge of CS , the device begins to power up and continues
to power up as long as CS is held low until after the falling edge
of the 10th SCLK. The device is fully powered up once at least
16 SCLKs (or approximately 6 μs) have elapsed and valid data
results from the next conversion as shown in
brought high before the 10th falling edge of SCLK, regardless of
the SCLK frequency, the AD7680 goes back into power-down
again. This avoids accidental power-up due to glitches on the
CS line or an inadvertent burst of 8 SCLK cycles while CS is low.
So although the device may begin to power-up on the falling
edge of CS , it powers down again on the rising edge of CS as
long as it occurs before the 10th SCLK falling edge.
10
1
THE PART IS FULLY POWERED
UP WITH V
THREE-STATE
IN
FULLY ACQUIRED
VALID DATA
20
Figure 18
20
AD7680
. If
CS is