AD7934-6 Analog Devices, AD7934-6 Datasheet - Page 25

• Manufacturer Part Number: AD7934-6
• Description: 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7934-6

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

POWER vs. THROUGHPUT RATE
A considerable advantage of powering the ADC down after a
conversion is that the part’s power consumption is significantly
reduced at lower throughput rates. When using the different
power modes, the AD7934-6 is only powered up for the
duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. Figure 39 shows
a plot of the power vs. the throughput rate when operating in
autostandby mode for both V
For example, if the device runs at a throughput rate of 10 kSPS,
the overall cycle time is 100 μs. If the maximum CLKIN
frequency of 10 MHz is used, the conversion time accounts for
only 1.315 μs of the overall cycle time while the AD7938-6 stays
in standby mode for the remainder of the cycle.
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7934-6 remains in standby for a
greater time in every cycle. Additionally, the current
consumption when converting should be lower than the
specified maximum of 1.5 mA or 1.2 mA with V
respectively.
Figure 40 shows a plot of the power vs. the throughput rate
when operating in normal mode for both V
Again, when using an external reference, the current
consumption when converting is lower than the specified
maximum. In both plots, Figure 39 and Figure 40 apply when
using the internal reference.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Figure 39. Power vs. Throughput in Autostandby Mode
0
0
T
A
= 25°C
20
Using Internal Reference
40
THROUGHPUT (kSPS)
DD
= 5 V and 3 V.
60
80
DD
V
V
DD
DD
= 5 V and 3 V.
= 5V
= 3V
DD
100
= 5 V or 3 V,
1
20
Rev. B | Page 25 of 28
MICROPROCESSOR INTERFACING
AD7934-6 to ADSP-21xx Interface
Figure 41 shows the AD7934-6 interfaced to the ADSP-21xx
series of DSPs as a memory-mapped device. A single wait state
could be necessary to interface the AD7934-6 to the ADSP-21xx,
depending on the clock speed of the DSP. The wait state can be
programmed via the data memory wait state control register of
the ADSP-21xx (see the ADSP-21xx family User’s Manual for
details). The following instruction reads from the AD7934-6:
where:
ADC is the address of the AD7934-6.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference
ADSP-21xx*
MR = DM (ADC)
A0 TO A15
D0 TO D23
7
6
5
4
3
2
1
0
0
IRQ2
DMS
T
WR
A
RD
= 25°C
Figure 41. Interfacing to the ADSP-21xx
100
ADDRESS BUS
ADDRESS
DECODER
DATA BUS
200
THROUGHPUT (kSPS)
300
400
500
V
V
DD
DD
DSP/USER SYSTEM
CS
BUSY
WR
RD
DB0 TO DB11
= 5V
= 3V
AD7934-6*
AD7934-6
CONVST
600
700