AD7765 Analog Devices, AD7765 Datasheet - Page 28

• Manufacturer Part Number: AD7765
• Description: 24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7765

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: 6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7765
AD7765 REGISTERS
The AD7765 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and
differential amplifier and provides an option to power down the AD7765. There are also digital gain and overrange threshold registers.
Writing to these registers involves writing the register address followed by a 16-bit data word. The register addresses, details of individual
bits, and default values are provided in this section.
CONTROL REGISTER
Table 13. Control Register (Address 0x0001, Default Value 0x0000)
MSB
D15
0
Table 14. Bit Descriptions of the Control Register
Bit
14
13
11
9
7
3
2
1
0
1
2
STATUS REGISTER
Table 15. Status Register (Read Only)
MSB
D15
PARTNO
Table 16. Bit Descriptions of the Status Register
Bit
15
10
9
8
4
3
2
1 to 0
Bit 14 to Bit 11 and Bit 9 are self-clearing bits.
Only one of the bits can be set in any write operation because it determines the contents of the next read operation.
Mnemonic
RD OVR
RD GAIN
RD STAT
SYNC
BYPASS REF
PWR DOWN
LPWR
REF BUF OFF
AMP OFF
D14
RD
OVR
D14
1
Mnemonic
PARTNO
FILTER-
SETTLE
0
OVR
REF BUF ON
AMP ON
LPWR
DEC[1:0]
1, 2
D13
RD
GAIN
D13
0
Comment
Read overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register
instead of a conversion result.
Read gain. If this bit is set, the next read operation outputs the contents of the digital gain register.
Read status. If this bit is set, the next read operation outputs the contents of the status register.
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple
devices synchronizes all filters.
Bypass reference. Setting this bit bypasses the reference buffer if the buffer is off.
Power-down. A logic high powers the device down without resetting. Writing a 0 to this bit powers the device back up.
Low power mode. Set to Logic 1 when AD7765 is in low power mode.
Reference buffer off. Asserting this bit powers down the reference buffer.
Amplifier off. Asserting this bit switches the differential amplifier off.
D12
0
Comment
Part number. This bit is set to 1 for the AD7765.
Filter settling bit. This bit corresponds to the FILTER-SETTLE bit in the status word output in the second 16-bit read
operation. It indicates when data is valid.
Zero. This bit is set to Logic 0.
Overrange. If the current analog input exceeds the current overrange threshold, this bit is set.
Reference buffer on. This bit is set when the reference buffer is in use.
Amplifier on. This bit is set when the input amplifier is in use.
Low power mode. This bit is set when operating in low power mode.
Decimation rate. These bits correspond to the decimation rate in use.
D12
0
D11
0
D11
RD
STAT
D10
FILTER-
SETTLE
0
D10
D9
SYNC
D9
0
D8
0
Rev. A | Page 28 of 32
D8
OVR
D7
BYPASS
REF
D7
0
D6
1
D6
0
D5
0
D5
0
D4
REF BUF
ON
D4
0
D3
PWR
DOWN
D3
AMP
ON
D2
LPWR
D2
LPWR
D1
REF BUF
OFF
D1
DEC 1
LSB
D0
AMP
OFF
LSB
D0
DEC 0